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95d12af
riscv: Replace __ASSEMBLY__ with __ASSEMBLER__ in uapi headers
huth Jun 6, 2025
d4332f0
riscv: Replace __ASSEMBLY__ with __ASSEMBLER__ in non-uapi headers
huth Jun 6, 2025
84338e4
Merge patch series "riscv: Replace __ASSEMBLY__ with __ASSEMBLER__ in…
Aug 11, 2025
8de4286
riscv: pi: use 'targets' instead of extra-y in Makefile
masahir0y Jun 2, 2025
42a4c00
riscv: cpufeature: add validation for zfa, zfh and zfhmin
clementleger May 27, 2025
df5443f
riscv: Fix typo EXRACT -> EXTRACT
Jun 20, 2025
9ac3f03
riscv: Strengthen duplicate and inconsistent definition of RV_X()
Jun 20, 2025
d97b515
riscv: Move all duplicate insn parsing macros into asm/insn.h
Jun 20, 2025
ce0024a
Merge patch series "Move duplicated instructions macros into asm/insn.h"
Aug 11, 2025
3589241
riscv: kprobes: Move branch_rs2_idx to insn.h
covanam May 14, 2025
4d316dd
riscv: kprobes: Move branch_funct3 to insn.h
covanam May 14, 2025
669a932
riscv: kprobes: Remove duplication of RV_EXTRACT_JTYPE_IMM
covanam May 14, 2025
a8ff3de
riscv: kprobes: Remove duplication of RV_EXTRACT_RS1_REG
covanam May 14, 2025
bf8d517
riscv: kprobes: Remove duplication of RV_EXTRACT_BTYPE_IMM
covanam May 14, 2025
6fdf1e7
riscv: kproves: Remove duplication of RVC_EXTRACT_JTYPE_IMM
covanam May 14, 2025
c51f624
riscv: kprobes: Remove duplication of RVC_EXTRACT_C2_RS1_REG
covanam May 14, 2025
f6bd3bb
riscv: kprobes: Remove duplication of RVC_EXTRACT_BTYPE_IMM
covanam May 14, 2025
dabcaeb
riscv: kprobes: Remove duplication of RV_EXTRACT_RD_REG
covanam May 14, 2025
124fe47
riscv: kprobes: Remove duplication of RV_EXTRACT_UTYPE_IMM
covanam May 14, 2025
cf9313d
riscv: kprobes: Remove duplication of RV_EXTRACT_ITYPE_IMM
covanam May 14, 2025
527fc52
Merge patch series "riscv: kprobes: Clean up instruction simulation"
Aug 11, 2025
dafeee9
riscv: Add kprobes KUnit test
covanam May 13, 2025
15e0d2d
riscv: mmap(): use unsigned offset type in riscv_sys_mmap
Jul 7, 2025
f6cde13
riscv: Move vendor errata definitions to new header
guoren83 Jul 13, 2025
d0f90db
riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup
guoren83 Jul 13, 2025
1dbdc7a
Merge patch series "riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup"
Aug 11, 2025
f04a7df
raid6: riscv: Clean up unused header file inclusion
Chunyan-iscas Jul 18, 2025
4d8f22d
raid6: riscv: replace one load with a move to speed up the caculation
Chunyan-iscas Jul 18, 2025
eb940a1
raid6: riscv: Prevent compiler with vector support to build already v…
Chunyan-iscas Jul 18, 2025
62c7eeb
raid6: riscv: Allow code to be compiled in userspace
Chunyan-iscas Jul 18, 2025
604128e
raid6: test: Add support for RISC-V
lyrazhang Jul 18, 2025
d75961a
Merge patch series "Add an optimization also raid6test for RISC-V sup…
Aug 11, 2025
6d335a4
riscv: mm: Return intended SATP mode for noXlvl options
pigmoral Jul 21, 2025
30b5e66
riscv: mm: Use mmu-type from FDT to limit SATP mode
pigmoral Jul 21, 2025
ee72ba7
Merge patch series "riscv: mm: Use mmu-type from FDT as SATP mode limit"
Aug 11, 2025
04b6f7f
riscv: Enable ARCH_HAVE_NMI_SAFE_CMPXCHG
Jul 11, 2025
6d7daa6
selftests: riscv: add misaligned access testing
clementleger Jul 11, 2025
66f89ae
riscv: introduce asm/swab.h
IEncinas10 Jul 23, 2025
166cfda
dt-bindings: riscv: Add xmipsexectl ISA extension description
aleksapaunovic-htec Jul 24, 2025
a6fc939
riscv: Add xmipsexectl as a vendor extension
aleksapaunovic-htec Jul 24, 2025
ccd1ca8
riscv: Add xmipsexectl instructions
aleksapaunovic-htec Jul 24, 2025
e6ba6c9
riscv: hwprobe: Add MIPS vendor extension probing
aleksapaunovic-htec Jul 24, 2025
0bfb32b
riscv: hwprobe: Document MIPS xmipsexectl vendor extension
aleksapaunovic-htec Jul 24, 2025
2fca07a
riscv: Add tools support for xmipsexectl
aleksapaunovic-htec Jul 24, 2025
52a44d8
riscv: errata: Fix the PAUSE Opcode for MIPS P8700
djtodoro Jul 24, 2025
0047666
Merge patch series "riscv: Add support for xmipsexectl"
Aug 11, 2025
957b938
RISC-V: ACPI: enable parsing the BGRT table
xypron Jul 29, 2025
effe4bf
ACPI: support BGRT table on RISC-V
xypron Jul 29, 2025
04e76f4
Merge patch series "ACPI: support BGRT table on RISC-V"
Aug 11, 2025
7d4f659
riscv: introduce ioremap_wc()
cuiyunhui Jul 22, 2025
66cb904
Adding CI files
Aug 11, 2025
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Binary file added .github/.MISSING_LINARO_DEP.swp
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Binary file added .github/.swp
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11 changes: 11 additions & 0 deletions .github/MISSING_LINARO_DEP
Original file line number Diff line number Diff line change
@@ -0,0 +1,11 @@
gdb (ltp vma05)
libnuma (ltp vma02-4)
swap file (swapping01)
fusermount (run_fuse_test.sh)
libfuse (run_fuse_test.sh)
mkisofs genisoimage xorrisofs (isofs.sh)
all modules (binfmt_misc0X)
mksquashfs
LTP_TIMEOUT_MUL > 1 (starvation)
libubsan ()
XXX (ltp-aiodio MUST be added)
Binary file added .github/scripts/.patches.sh.swp
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30 changes: 30 additions & 0 deletions .github/scripts/build_ubuntu_defconfig.sh
Original file line number Diff line number Diff line change
@@ -0,0 +1,30 @@
#!/bin/bash
# SPDX-FileCopyrightText: 2024 Rivos Inc.
#
# SPDX-License-Identifier: Apache-2.0

set -euox pipefail
d=$(dirname "${BASH_SOURCE[0]}")
. $d/series/utils.sh

logs=$(get_logs_dir)
f=${logs}/build_ubuntu_defconfig.log

date -Iseconds | tee -a ${f}
echo "Build an ubuntu kernel" | tee -a ${f}
echo "Top 16 commits" | tee -a ${f}
git log -16 --abbrev=12 --pretty="commit %h (\"%s\")" | tee -a ${f}

kernel_base_sha=$(git log -1 --pretty=%H $(git log -1 --reverse --pretty=%H .github)^)
build_name=$(git describe --tags --abbrev=13 ${kernel_base_sha})
echo "build_name ${build_name}" | tee -a ${f}

# Build the kernel that will run LTP
export CI_TRIPLE="riscv64-linux-gnu"
# Use a CFI-enabled toolchain
export PATH=/build/INSTALL_Sept24/bin:$PATH
cp $d/series/kconfigs/ubuntu_defconfig arch/riscv/configs/
$d/series/kernel_builder.sh rv64 testsuites plain gcc | tee -a ${f}

kernel_dir="/build/$(gen_kernel_name rv64 testsuites plain gcc)"
echo $build_name > $kernel_dir/kernel_version
2 changes: 2 additions & 0 deletions .github/scripts/ci/__init__.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,2 @@
from .base import Base, EndTest, Verdict, submit_pw_check
from .shelltest import ShellTest
120 changes: 120 additions & 0 deletions .github/scripts/ci/base.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,120 @@
from abc import ABC, abstractmethod
from enum import Enum
import time
import sys

from libs import utils

sys.path.insert(0, '../libs')
from libs import log_debug

class Verdict(Enum):
PENDING = 0
PASS = 1
FAIL = 2
ERROR = 3
SKIP = 4
WARNING = 5


class EndTest(Exception):
"""
End of Test
"""

class Base(ABC):
"""
Base class for CI Tests.
"""
def __init__(self):
self.start_time = 0
self.end_time = 0
self.verdict = Verdict.PENDING
self.output = ""

def success(self):
self.end_timer()
self.verdict = Verdict.PASS

def error(self, msg):
self.verdict = Verdict.ERROR
self.output = msg
self.end_timer()
raise EndTest

def warning(self, msg):
self.verdict = Verdict.WARNING
self.output = msg
self.end_timer()

def skip(self, msg):
self.verdict = Verdict.SKIP
self.output = msg
self.end_timer()
raise EndTest

def add_failure(self, msg):
self.verdict = Verdict.FAIL
if not self.output:
self.output = msg
else:
self.output += "\n" + msg

def add_failure_end_test(self, msg):
self.add_failure(msg)
self.end_timer()
raise EndTest

def start_timer(self):
self.start_time = time.time()

def end_timer(self):
self.end_time = time.time()

def elapsed(self):
if self.start_time == 0:
return 0
if self.end_time == 0:
self.end_timer()
return self.end_time - self.start_time

def log_err(self, msg):
utils.log_error(f"CI: {self.name}: {msg}")

def log_info(self, msg):
utils.log_info(f"CI: {self.name}: {msg}")

def log_dbg(self, msg):
utils.log_debug(f"CI: {self.name}: {msg}")

@abstractmethod
def run(self, worktree=None):
"""
The child class should implement run() method
If the test fail, it should raise the EndTest exception
"""
pass

@abstractmethod
def post_run(self):
"""
The child class should implement post_run() method
"""
pass


def submit_pw_check(pw, patch, name, verdict, desc, url=None, dry_run=False):

utils.log_debug(f"Submitting the result to PW: dry_run={dry_run}")

if not dry_run:
state = 0

if verdict == Verdict.PASS:
state = 1
if verdict == Verdict.WARNING:
state = 2
if verdict == Verdict.FAIL:
state = 3

pw.post_check(patch, name, state, desc, url)
67 changes: 67 additions & 0 deletions .github/scripts/ci/shelltest.py
Original file line number Diff line number Diff line change
@@ -0,0 +1,67 @@
from gettext import install
import os
import sys

sys.path.insert(0, '../libs')
from libs import RepoTool, cmd_run

from ci import Base, Verdict, EndTest, submit_pw_check

class ShellTest(Base):
"""Run shell test class
This class runs a shell based test
"""

def __init__(self, ci_data, patch, name, desc, sh):

# Common
self.name = name
self.desc = desc
self.ci_data = ci_data

self.sh = sh
self.patch = patch

super().__init__()

self.log_dbg("Initialization completed")

def run(self, worktree=None):

self.log_dbg("Run")
self.start_timer()

current_script_path = os.path.dirname(os.path.abspath(__file__))

cwd = worktree if worktree else self.ci_data.src_dir
cmd = ["bash", f"{current_script_path}/../pw_tests/{self.sh}"]
(ret, stdout, stderr) = cmd_run(cmd, cwd=cwd)

if ret == 0:
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.PASS,
self.name,
None, self.ci_data.config['dry_run'])
self.success()
elif ret == 250:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-WARNING",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.WARNING,
self.name,
url, self.ci_data.config['dry_run'])
self.warning(stdout + '\n' + stderr)
else:
url = self.ci_data.gh.create_gist(f"pw{self.ci_data.series['id']}-p{self.patch['id']}",
f"{self.name}-FAIL",
stdout + '\n' + stderr)
submit_pw_check(self.ci_data.pw, self.patch,
self.name, Verdict.FAIL,
self.name,
url, self.ci_data.config['dry_run'])
self.error(stdout + '\n' + stderr)

def post_run(self):

self.log_dbg("Post Run...")
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