[PW_SID:1129940] irqchip/riscv-imsic: Use GENMASK for base address masks#2311
[PW_SID:1129940] irqchip/riscv-imsic: Use GENMASK for base address masks#2311linux-riscv-bot wants to merge 2 commits into
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The IMSIC DT binding allows riscv,guest-index-bits up to 7 and riscv,hart-index-bits up to 15. On RV32, guest-index-bits=7 and hart-index-bits=13, together with the 12-bit IMSIC page offset, is a binding-valid layout that consumes a 32-bit low-address mask. The parser accepts this equality case because it rejects only values larger than the remaining bit budget. The base address canonicalization then builds the low-address mask with BIT(sum) - 1. When sum is 32 on RV32, that expression shifts an unsigned long by its full width. Keep the legal equality layout and express the mask with GENMASK(sum - 1, 0) instead. The existing parser bounds guarantee that sum - 1 is below BITS_PER_LONG at both mask sites. Fixes: 21a8f8a ("irqchip: Add RISC-V incoming MSI controller early driver") Signed-off-by: Pengpeng Hou <pengpeng@iscas.ac.cn> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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Patch 1: "irqchip/riscv-imsic: Use GENMASK for base address masks" |
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PR for series 1129940 applied to workflow__riscv__fixes
Name: irqchip/riscv-imsic: Use GENMASK for base address masks
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1129940
Version: 1