[PW_SID:1126629] [v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers#2272
[PW_SID:1126629] [v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers#2272linux-riscv-bot wants to merge 2 commits into
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The RISC-V IOMMU specification [1] permits 64-bit registers to be accessed using two 32-bit transactions, high half first, and leaves the single-copy atomicity of 8-byte IOMMU register accesses unspecified. Use the generic hi_lo_readq_relaxed() and hi_lo_writeq_relaxed() helpers for ordinary 64-bit IOMMU registers. For DDTP, poll BUSY in the low half, then read the high half and compose the register value from the polled low half. HPM counter reads require a rollover-aware sequence and remain outside these accessors. This follows the 32-bit access direction proposed by Guo Ren [2] and uses the generic non-atomic MMIO helpers suggested by David Laight. [1] https://docs.riscv.org/reference/iommu/ [2] https://lore.kernel.org/r/20250903144217.837448-1-guoren@kernel.org Suggested-by: Guo Ren <guoren@kernel.org> Suggested-by: David Laight <david.laight.linux@gmail.com> Signed-off-by: Zhanpeng Zhang <zhangzhanpeng.jasper@bytedance.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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Patch 1: "[v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers" |
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PR for series 1126629 applied to workflow__riscv__fixes
Name: [v3] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1126629
Version: 3