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[PW_SID:1126315] [v2] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers #2266

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[PW_SID:1126315] [v2] iommu/riscv: Use 32-bit MMIO accesses for 64-bit registers #2266

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18 changes: 11 additions & 7 deletions drivers/iommu/riscv/iommu.c
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Original file line number Diff line number Diff line change
Expand Up @@ -668,12 +668,16 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu)
riscv_iommu_writel(iommu, RISCV_IOMMU_REG_PQCSR, 0);
}

#define riscv_iommu_read_ddtp(iommu) ({ \
u64 ddtp; \
riscv_iommu_readq_timeout((iommu), RISCV_IOMMU_REG_DDTP, ddtp, \
!(ddtp & RISCV_IOMMU_DDTP_BUSY), 10, \
RISCV_IOMMU_DDTP_TIMEOUT); \
ddtp; })
static u64 riscv_iommu_read_ddtp(struct riscv_iommu_device *iommu)
{
u32 ddtp_lo;

riscv_iommu_readl_timeout(iommu, RISCV_IOMMU_REG_DDTP, ddtp_lo,
!(ddtp_lo & RISCV_IOMMU_DDTP_BUSY), 10,
RISCV_IOMMU_DDTP_TIMEOUT);

return riscv_iommu_readq(iommu, RISCV_IOMMU_REG_DDTP);
}

static int riscv_iommu_iodir_alloc(struct riscv_iommu_device *iommu)
{
Expand Down Expand Up @@ -1501,7 +1505,7 @@ static int riscv_iommu_init_check(struct riscv_iommu_device *iommu)
* regular boot flow and disable translation when we boot into a kexec
* kernel and the previous kernel left them enabled.
*/
ddtp = riscv_iommu_readq(iommu, RISCV_IOMMU_REG_DDTP);
ddtp = riscv_iommu_read_ddtp(iommu);
if (ddtp & RISCV_IOMMU_DDTP_BUSY)
return -EBUSY;

Expand Down
9 changes: 3 additions & 6 deletions drivers/iommu/riscv/iommu.h
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Original file line number Diff line number Diff line change
Expand Up @@ -11,6 +11,7 @@
#ifndef _RISCV_IOMMU_H_
#define _RISCV_IOMMU_H_

#include <linux/io-64-nonatomic-hi-lo.h>
#include <linux/iommu.h>
#include <linux/types.h>
#include <linux/iopoll.h>
Expand Down Expand Up @@ -70,17 +71,13 @@ void riscv_iommu_disable(struct riscv_iommu_device *iommu);
readl_relaxed((iommu)->reg + (addr))

#define riscv_iommu_readq(iommu, addr) \
readq_relaxed((iommu)->reg + (addr))
hi_lo_readq_relaxed((iommu)->reg + (addr))

#define riscv_iommu_writel(iommu, addr, val) \
writel_relaxed((val), (iommu)->reg + (addr))

#define riscv_iommu_writeq(iommu, addr, val) \
writeq_relaxed((val), (iommu)->reg + (addr))

#define riscv_iommu_readq_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
readx_poll_timeout(readq_relaxed, (iommu)->reg + (addr), val, cond, \
delay_us, timeout_us)
hi_lo_writeq_relaxed((val), (iommu)->reg + (addr))

#define riscv_iommu_readl_timeout(iommu, addr, val, cond, delay_us, timeout_us) \
readx_poll_timeout(readl_relaxed, (iommu)->reg + (addr), val, cond, \
Expand Down