[PW_SID:1122610] [v3] RISC-V: KVM: Zicbo[m|z|p] block sizes should be always present in ONE_REG#2230
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[PW_SID:1122610] [v3] RISC-V: KVM: Zicbo[m|z|p] block sizes should be always present in ONE_REG#2230linux-riscv-bot wants to merge 2 commits into
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…_REG All config and core registers of the KVM RISC-V ONE_REG interface are expected to be always available to the KVM user-space and the KVM get-reg-list selftest assumes these registers to be as base registers. Currently, the Zicbo[m|z|p] block size config registers are only available when corresponding ISA extension is present on the host which breaks the above expectation. In fact, KVM get-reg-list selftest fails when any of the Zicbo[m|z|p] ISA extension is not present on host. To address this issue, drop the ISA extension checks from kvm_riscv_vcpu_get/set_reg_config() and copy_config_reg_indices() functions. Fixes: 031f9ef ("KVM: riscv: Add KVM_GET_REG_LIST API support") Fixes: a044ef7 ("RISC-V: KVM: use ENOENT in *_one_reg() when extension is unavailable") Fixes: 48e2feb ("RISC-V: KVM: Provide UAPI for Zicbop block size") Fixes: cf05b05 ("RISC-V: KVM: Introduce common kvm_riscv_isa_check_host()") Signed-off-by: Anup Patel <anup.patel@oss.qualcomm.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>
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PR for series 1122610 applied to workflow__riscv__fixes
Name: [v3] RISC-V: KVM: Zicbo[m|z|p] block sizes should be always present in ONE_REG
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1122610
Version: 3