[PW_SID:1119805] riscv: hwprobe: Expose RVA23U64 base behavior by linux-riscv-bot · Pull Request #2192 · linux-riscv/linux

linux-riscv-bot · 2026-07-01T14:19:43Z

PR for series 1119805 applied to workflow__riscv__fixes

Name: riscv: hwprobe: Expose RVA23U64 base behavior
URL: https://patchwork.kernel.org/project/linux-riscv/list/?series=1119805
Version: 5

The multi-letter extension enum is documented as being sorted alphanumerically (see the "multi-letter extensions, sorted alphanumerically" comment), but several Z entries have drifted out of order. Reorder the affected entries so the multi-letter Z list is sorted alphanumerically again. Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

A handful of vendor-extension entries indent continuation lines with a tab character, while the rest of hwprobe.rst uses spaces. In addition, many list items align their continuation lines under the 'm' of ':c:macro:' (column 7) rather than under the item text (column 4), so the file mixes several indentation styles. Replace the tabs with spaces and align every list item's continuation lines under the item text, giving the whole file one consistent style. Whitespace-only change, no functional change. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> [Guodong: extend from tabs->spaces to normalizing all continuation-line indentation across the file] Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

RISCV_HWPROBE_EXT_ZICFISS and RISCV_HWPROBE_EXT_ZICFILP are defined in the hwprobe uAPI but are not documented in Documentation/arch/riscv/hwprobe.rst. Add documentation for them. Link: riscv/riscv-cfi@302a2d4 Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

The base extensions are often lowercase and were written as lowercase in hwcap, but other references to these extensions in the kernel are uppercase. Standardize the case to make it easier to handle macro expansion. Acked-by: Anup Patel <anup@brainfault.org> Reviewed-by: Anup Patel <anup@brainfault.org> Signed-off-by: Charlie Jenkins <thecharlesjenkins@gmail.com> [Apply KVM_ISA_EXT_ARR(), fixup all KVM use.] Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Zicclsm requires misaligned support for all regular load and store instructions, both scalar and vector, but not AMOs or other specialized forms of memory access, to main memory regions with both the cacheability and coherence PMAs, as defined in the profiles spec. Even though mandated, misaligned loads and stores might execute extremely slowly. Standard software distributions should assume their existence only for correctness, not for performance. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Reviewed-by: Andy Chiu <andy.chiu@sifive.com> Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Tested-by: Charlie Jenkins <charlie@rivosinc.com> Signed-off-by: Jesse Taube <jesse@rivosinc.com> [Rebased, rewrote doc text, minor commit message revisions] Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

…probe Add Ziccamoa, Ziccif, and Za64rs to riscv_isa_ext[] so they can be parsed from devicetree/ACPI ISA strings. Ziccrse is already present in cpufeature; this patch only adds its hwprobe exposure. Expose all four extensions via hwprobe through new bits in RISCV_HWPROBE_KEY_IMA_EXT_1 (RISCV_HWPROBE_EXT_ZICCAMOA, _ZICCIF, _ZICCRSE, _ZA64RS), so userspace can probe each of these RVA23U64-mandatory extensions individually. Reviewed-by: Jesse Taube <jtaubepe@redhat.com> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Add B to hwcap and ensure when B is present that Zba, Zbb, and Zbs are all set. Also expose B via hwprobe (RISCV_HWPROBE_EXT_B in RISCV_HWPROBE_KEY_IMA_EXT_1) so that userspace can probe B directly, mirroring the F/D/C/V pattern where each is reported via both hwcap and hwprobe. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> [Add B to hwprobe] Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Zicbom, Zicbop, and Zicboz have no default cache block size, so a devicetree that declares one must also provide the matching riscv,cbom/cbop/cboz-block-size property. Make it required so a missing block-size property can be caught by dtbs_check. Suggested-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Zic64b mandates that cache blocks are 64 bytes in size and naturally aligned in the address space. It is a mandatory extension of both the RVA22 (U64/S64) and RVA23 (U64/S64) profiles, ratified with RISC-V Profiles Version 1.0. Document it so it can be described in the riscv,isa-extensions property, alongside the related Zicbom/Zicbop/Zicboz cache-block extensions. Since Zic64b fixes the cache block size at 64 bytes, also add a schema check requiring any present cbom/cbop/cboz block size to be 64. Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Zic64b mandates 64-byte naturally aligned cache blocks and is a mandatory extension of the RVA22 and RVA23 profiles. Allocate a RISCV_ISA_EXT_ZIC64B id, parse "zic64b" from the ISA string with a validate callback that requires each cbom/cbop/cboz cache block size to be 64 bytes when it is present, and export it through hwprobe. Link: https://lists.riscv.org/g/tech-unprivileged/topic/question_about_zic64b_and/119631059 Reviewed-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Qingwei Hu <qingwei.hu@bytedance.com> Co-developed-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

The K3 X100 cores have 64-byte cache blocks, already described by their cbom/cbop/cboz-block-size of 64, so they implement Zic64b, a mandatory RVA23 extension. Declare it in each core's riscv,isa-extensions. Reviewed-by: Yixun Lan <dlan@kernel.org> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

The K1 X60 cores have 64-byte cache blocks, described by their cbom/cbop/cboz-block-size of 64, so they implement Zic64b. Declare it in each core's riscv,isa-extensions and in the deprecated riscv,isa string. Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

The SG2044 cores have 64-byte cache blocks, described by their cbom/cbop/cboz-block-size of 64, so they implement Zic64b. Declare it in each core's riscv,isa-extensions. Acked-by: Inochi Amaoto <inochiama@gmail.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Querying whether a given user PMLEN is supported is needed for RVA23U64 base detection from outside arch/riscv/kernel/process.c. Add riscv_have_user_pmlen() to expose this. Link: https://lore.kernel.org/linux-riscv/rfuwa7a3ebe76udmnwyrssjy7shkkgxntvhwzn6oquysj4tuyp@xzvpylcfhz53/ Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> [Guodong: replace exported booleans with getter per Andrew's suggestion] Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Introduce a per-hart and host-wide bitmap of conformant ISA "bases" (named profile-class sets such as IMA and RVA23U64), computed at init time by riscv_init_isa_bases(). Register riscv_init_isa_bases() as a subsys_initcall so it executes after core_initcall(tagged_addr_init), which probes senvcfg.PMM and populates have_user_pmlen_*. Without that ordering, riscv_have_user_pmlen(7) would still return its default false and the RVA23U64 detection path would always bail. Consider this as the cache that subsequent consumers (hwprobe's RVA23U64 base behavior bit, /proc/cpuinfo's "isa bases" lines, etc.) can read without recomputing. System-wide consistency are ensured. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

The "isa" line in /proc/cpuinfo lists a hart's extensions as concatenated string, but not which profile base it satisfies. Add two lines that report them directly: isa bases : <bases that all harts conform to> hart isa bases : <bases that this specific hart conforms to> Example output on qemu booted with -cpu rva23s64,sv39=on,pmp=on: processor : 0 hart : 4 isa bases : rv64ima rva23u64 isa : rv64imafdcbvh_zicbom_zicbop_... ... hart isa bases : rv64ima rva23u64 hart isa : rv64imafdcbvh_zicbom_zicbop_... Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

Provide a hwprobe base-behavior bit so userspace can check RVA23U64 support in one call. Without it, a consumer needs five hwprobe calls and four prctl calls, which is error-prone to require of every caller. Most software treats RVA23U64 as a new base anyway, so expose it directly. Signed-off-by: Andrew Jones <andrew.jones@oss.qualcomm.com> Signed-off-by: Guodong Xu <docular.xu@gmail.com> Signed-off-by: Linux RISC-V bot <linux.riscv.bot@gmail.com>

linux-riscv-bot · 2026-07-01T15:45:47Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 151.50 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:05:06Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1157.21 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:29:27Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1459.64 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:29:58Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 29.86 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:30:31Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 30.78 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:30:33Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.73 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:32:02Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 87.59 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:32:05Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.65 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:32:07Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
kdoc
Desc: Detects for kdoc errors
Duration: 0.89 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:32:09Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
module-param
Desc: Detect module_param changes
Duration: 0.27 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:32:11Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.24 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:32:13Z

Patch 1: "[v5,01/17] dt-bindings: riscv: sort multi-letter Z extensions alphanumerically"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.33 seconds
Result: PASS

linux-riscv-bot · 2026-07-01T16:35:01Z

Patch 2: "[v5,02/17] riscv: hwprobe.rst: Make indentation consistent"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 151.97 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T08:38:42Z

Patch 15: "[v5,15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 90.12 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T08:38:44Z

Patch 15: "[v5,15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 1.00 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T08:38:47Z

Patch 15: "[v5,15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection"
kdoc
Desc: Detects for kdoc errors
Duration: 1.18 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T08:38:49Z

Patch 15: "[v5,15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection"
module-param
Desc: Detect module_param changes
Duration: 0.77 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T08:38:51Z

Patch 15: "[v5,15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.95 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T08:38:56Z

Patch 15: "[v5,15/17] riscv: cpufeature: Introduce ISA bases bitmap and rva23u64 detection"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 3.51 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T08:41:46Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 154.05 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:05:41Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1433.10 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:34:54Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1751.46 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:35:25Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 29.64 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:35:57Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 30.60 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:36:00Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 0.74 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:37:28Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 87.06 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:37:30Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:37:32Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
kdoc
Desc: Detects for kdoc errors
Duration: 0.91 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:37:34Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
module-param
Desc: Detect module_param changes
Duration: 0.25 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:37:36Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.21 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:37:38Z

Patch 16: "[v5,16/17] riscv: cpu: Output isa bases lines in cpuinfo"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.34 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T09:40:25Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
build-rv32-defconfig
Desc: Builds riscv32 defconfig
Duration: 151.96 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:05:11Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
build-rv64-clang-allmodconfig
Desc: Builds riscv64 allmodconfig with Clang, and checks for errors and added warnings
Duration: 1484.70 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:35:01Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
build-rv64-gcc-allmodconfig
Desc: Builds riscv64 allmodconfig with GCC, and checks for errors and added warnings
Duration: 1788.28 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:35:32Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
build-rv64-nommu-k210-defconfig
Desc: Builds riscv64 defconfig with NOMMU for K210
Duration: 29.60 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:36:04Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
build-rv64-nommu-k210-virt
Desc: Builds riscv64 defconfig with NOMMU for the virt platform
Duration: 30.06 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:36:07Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
checkpatch
Desc: Runs checkpatch.pl on the patch
Duration: 2.29 seconds
Result: WARNING
Output:

CHECK: Prefer using the BIT macro
#50: FILE: arch/riscv/include/uapi/asm/hwprobe.h:24:
+#define		RISCV_HWPROBE_BASE_BEHAVIOR_IMA		(1 << 0)

CHECK: Prefer using the BIT macro
#51: FILE: arch/riscv/include/uapi/asm/hwprobe.h:25:
+#define		RISCV_HWPROBE_BASE_BEHAVIOR_RVA23U64	(1 << 1)

total: 0 errors, 0 warnings, 2 checks, 67 lines checked

NOTE: For some of the reported defects, checkpatch may be able to
      mechanically convert to the typical style using --fix or --fix-inplace.

Commit afaf6e62c4a9 ("riscv: hwprobe: Introduce rva23u64 base behavior") has style problems, please review.

NOTE: Ignored message types: ALLOC_SIZEOF_STRUCT CAMELCASE COMMIT_LOG_LONG_LINE GIT_COMMIT_ID MACRO_ARG_REUSE NO_AUTHOR_SIGN_OFF

NOTE: If any of the errors are false positives, please report
      them to the maintainer, see CHECKPATCH in MAINTAINERS.
total: 0 errors, 0 warnings, 2 checks, 67 lines checked
CHECK: Prefer using the BIT macro

linux-riscv-bot · 2026-07-02T10:37:35Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
dtb-warn-rv64
Desc: Checks for Device Tree warnings/errors
Duration: 85.71 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:37:37Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
header-inline
Desc: Detects static functions without inline keyword in header files
Duration: 0.23 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:37:39Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
kdoc
Desc: Detects for kdoc errors
Duration: 0.92 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:37:41Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
module-param
Desc: Detect module_param changes
Duration: 0.26 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:37:42Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
verify-fixes
Desc: Verifies that the Fixes: tags exist
Duration: 0.22 seconds
Result: PASS

linux-riscv-bot · 2026-07-02T10:37:44Z

Patch 17: "[v5,17/17] riscv: hwprobe: Introduce rva23u64 base behavior"
verify-signedoff
Desc: Verifies that Signed-off-by: tags are correct
Duration: 0.33 seconds
Result: PASS

docularxu and others added 17 commits July 1, 2026 14:19

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

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linux-riscv-bot commented Jul 2, 2026

Uh oh!

linux-riscv-bot commented Jul 2, 2026

Uh oh!