[PW_SID:1119561] Add Counter delegation ISA extension support#2185

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linux-riscv-bot wants to merge 22 commits into

workflow__riscv__fixesfrom

pw1119561

Commits on Jul 1, 2026

RISC-V: perf: fix resource cleanup on driver probe failure

Atish Patra
authored and
Linux RISC-V bot
committed
RISC-V: Add Sxcsrind ISA extension CSR definitions

KevinRSX
authored and
Linux RISC-V bot
committed
RISC-V: Add Sxcsrind ISA extension definition and parsing

atishp04
authored and
Linux RISC-V bot
committed
dt-bindings: riscv: add Sxcsrind ISA extension description

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: Define indirect CSR access helpers

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: Add Smcntrpmf extension parsing

atishp04
authored and
Linux RISC-V bot
committed
dt-bindings: riscv: add Smcntrpmf ISA extension description

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: Add Sscfg extension CSR definition

KevinRSX
authored and
Linux RISC-V bot
committed
RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing

atishp04
authored and
Linux RISC-V bot
committed
dt-bindings: riscv: add Counter delegation ISA extensions description

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: perf: Restructure the SBI PMU code

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: perf: Modify the counter discovery mechanism

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: perf: Add a mechanism to defined legacy event encoding

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: perf: Implement supervisor counter delegation support

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: perf: Skip PMU SBI extension when not implemented

charlie-rivos
authored and
Linux RISC-V bot
committed
RISC-V: perf: Use config2/vendor table for event to counter mapping

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: perf: Add legacy event encodings via sysfs

atishp04
authored and
Linux RISC-V bot
committed
RISC-V: perf: Add Qemu virt machine events

atishp04
authored and
Linux RISC-V bot
committed
tools/perf: Support event code for arch standard events

atishp04
authored and
Linux RISC-V bot
committed
tools/perf: Add RISC-V CounterIDMask event field

atishp04
authored and
Linux RISC-V bot
committed
TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing

Atish Patra
authored and
Linux RISC-V bot
committed
TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path

Atish Patra
authored and
Linux RISC-V bot
committed

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[PW_SID:1119561] Add Counter delegation ISA extension support#2185

[PW_SID:1119561] Add Counter delegation ISA extension support#2185
linux-riscv-bot wants to merge 22 commits into
workflowriscvfixesfrom
pw1119561

Commits on Jul 1, 2026

RISC-V: perf: fix resource cleanup on driver probe failure

RISC-V: Add Sxcsrind ISA extension CSR definitions

RISC-V: Add Sxcsrind ISA extension definition and parsing

dt-bindings: riscv: add Sxcsrind ISA extension description

RISC-V: Define indirect CSR access helpers

RISC-V: Add Smcntrpmf extension parsing

dt-bindings: riscv: add Smcntrpmf ISA extension description

RISC-V: Add Sscfg extension CSR definition

RISC-V: Add Ssccfg/Smcdeleg ISA extension definition and parsing

dt-bindings: riscv: add Counter delegation ISA extensions description

RISC-V: perf: Restructure the SBI PMU code

RISC-V: perf: Modify the counter discovery mechanism

RISC-V: perf: Add a mechanism to defined legacy event encoding

RISC-V: perf: Implement supervisor counter delegation support

RISC-V: perf: Skip PMU SBI extension when not implemented

RISC-V: perf: Use config2/vendor table for event to counter mapping

RISC-V: perf: Add legacy event encodings via sysfs

RISC-V: perf: Add Qemu virt machine events

tools/perf: Support event code for arch standard events

tools/perf: Add RISC-V CounterIDMask event field

TEST(do-not-upstream): fake qemu-virt PMU events for cdeleg counter-mask testing

TEST(do-not-upstream): fake qemu vendor JSON + mapfile entry for CounterIDMask path