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[PW_SID:1119026] clk: spacemit: Add clock support for UFS #2176

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[PW_SID:1119026] clk: spacemit: Add clock support for UFS #2176

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418a6df
clk: spacemit: k3: fix parent clock of UFS aclk
Jun 30, 2026
479a7b4
dt-bindings: soc: spacemit: k3: Add clock ID for UFS refclk
Jun 30, 2026
5be15ea
clk: spacemit: k3: Add UFS refclk clock
Jun 30, 2026
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10 changes: 6 additions & 4 deletions drivers/clk/spacemit/ccu-k3.c
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Original file line number Diff line number Diff line change
Expand Up @@ -926,15 +926,16 @@ CCU_MUX_DIV_GATE_FC_DEFINE(dpu_aclk, dpu_aclk_parents, APMU_LCD_CLK_RES_CTRL5, 1
20, 3, BIT(16), 0);

static const struct clk_parent_data ufs_aclk_parents[] = {
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll1_d5_491p52),
CCU_PARENT_HW(pll1_d4_614p4),
CCU_PARENT_HW(pll1_d8_307p2),
CCU_PARENT_HW(pll2_d4),
CCU_PARENT_HW(pll1_d6_409p6),
CCU_PARENT_HW(pll2_d6),
CCU_PARENT_HW(pll2_d5),
};
CCU_MUX_DIV_GATE_FC_DEFINE(ufs_aclk, ufs_aclk_parents, APMU_UFS_CLK_RES_CTRL, 5, 3, BIT(8),
2, 3, BIT(1), 0);

CCU_FACTOR_DEFINE(ufs_refclk, CCU_PARENT_HW(pll1_d64_38p4), 2, 1);

static const struct clk_parent_data edp0_pclk_parents[] = {
CCU_PARENT_HW(lcd_pxclk),
CCU_PARENT_NAME(external_clk),
Expand Down Expand Up @@ -1392,6 +1393,7 @@ static struct clk_hw *k3_ccu_apmu_hws[] = {
[CLK_APMU_DSI4LN2_DPU_ACLK] = &dsi4ln2_dpu_aclk.common.hw,
[CLK_APMU_DPU_ACLK] = &dpu_aclk.common.hw,
[CLK_APMU_UFS_ACLK] = &ufs_aclk.common.hw,
[CLK_APMU_UFS_REFCLK] = &ufs_refclk.common.hw,
[CLK_APMU_EDP0_PXCLK] = &edp0_pxclk.common.hw,
[CLK_APMU_EDP1_PXCLK] = &edp1_pxclk.common.hw,
[CLK_APMU_PCIE_PORTA_MSTE] = &pciea_mstr_clk.common.hw,
Expand Down
1 change: 1 addition & 0 deletions include/dt-bindings/clock/spacemit,k3-clocks.h
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Original file line number Diff line number Diff line change
Expand Up @@ -385,6 +385,7 @@
#define CLK_APMU_PCIE_PORTC_DBI 91
#define CLK_APMU_PCIE_PORTD_DBI 92
#define CLK_APMU_PCIE_PORTE_DBI 93
#define CLK_APMU_UFS_REFCLK 94

/* DCIU clocks */
#define CLK_DCIU_HDMA 0
Expand Down