I'm Joey, a UC Irvine Alum and Hardware Engineer. I'm always learning and I love doing small projects outside of my regular work.
- I love building computers, I've built nine so far!
- The first programming language I learned was Python (but C is my favorite!).
- I enjoy running, surfing, and playing guitar in my free time.
- Ayar Labs
- System Hardware Engineer | March 2026 - Present (4 months)
- Cisco Systems
- Hardware Engineer | June 2024 - March 2026 (1 year, 10 months)
- Hardware Engineer Intern | June 2022 - September 2022, June 2023 - June 2024 (1 year, 3 months)
- Silicon Photonics
- Co-Packaged Optics (CPO)
- Mixed Signal ICs
- VLSI Layout
- Cadence - advanced CMOS circuits
- RTL Design
- Verilog/SystemVerilog - hardware controllers, design verification
- Silicon Bring-Up
- DVT/Production - high-speed optical transcievers
- Processor Architecture
- Scalar, pipelined RISC-V and MIPS32 microarchitectures
- Vector accelerator, RISC-V ISA compliant
- Bare-Metal Programming
- TI MCUs - chipset firmware
- ST MCUs - product-level and chipset firmware
- Arduino/ESP32 MCUs - low-cost lab tools
- C/C++ - GUIs, threaded applications, embedded firmware
- Python - GUIs, data analysis, machine learning, digital signal processing, multi-threaded applications, production-level software packages
- Java - GUIs, server-side software modules
- C# - production-level software packages
- Assembly (x86) - inline assembly, binary reverse engineering, memory manipulation
- Assembly (RISC-V/MIPS32) - processor design, ISA implementation, inline assembly