An in-situ debugging framework for hardware design.
python3 software/compile.py examples/blink/blinker.py-
Yosys, the Verilog synthesizer
-
Nextpnr, a place-and-route tool
-
Project Trellis, toolchain for ECP5 FPGAs
hardware/: Any RTL required for HDDB lives here.
software/: The HDDB client and compiler live here.
examples/: RTL examples along with client software for driving the examples live here.