GitHub - jaitrived123456789/-AND_Gate_Verification: AND_Gate_Verification Test Strategy • Random Testing: Generate randomized inputs to cover all scenarios. • Functional Coverage: (Optional enhancement) Track coverage of all input combinations. • Self-Checking: Scoreboard automatically checks and logs pass/fail. ModelSim (SE-64),SystemVerilog, Command line (vsim -c) or GUI (vsim -gui)

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Name		Name	Last commit message	Last commit date
Latest commit History 1 Commit
env		env
rtl		rtl
sim		sim
tb		tb
work		work
Hirearchy_Print.jpeg		Hirearchy_Print.jpeg
Objective of the Project.txt		Objective of the Project.txt
Research done for AND gate Verification.docx		Research done for AND gate Verification.docx
Run Commands.txt		Run Commands.txt
TB_architecture.txt		TB_architecture.txt
V_plan.docx		V_plan.docx
Waveform.JPG		Waveform.JPG
What we have done.txt		What we have done.txt
and_if.v		and_if.v
and_pkg.sv		and_pkg.sv
my_and.v		my_and.v
tcl_stacktrace.txt		tcl_stacktrace.txt
transcript		transcript
vsim.wlf		vsim.wlf
vsim_stacktrace.vstf		vsim_stacktrace.vstf

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AND_Gate_Verification Test Strategy • Random Testing: Generate randomized inputs to cover all scenarios. • Functional Coverage: (Optional enhancement) Track coverage of all input combinations. • Self-Checking: Scoreboard automatically checks and logs pass/fail. ModelSim (SE-64),SystemVerilog, Command line (vsim -c) or GUI (vsim -gui)

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