build(deps): bump hw/deps/litex from 4f82a36 to e0d5a7b#323
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build(deps): bump hw/deps/litex from 4f82a36 to e0d5a7b#323dependabot-preview[bot] wants to merge 1 commit into
4f82a36 to e0d5a7b#323dependabot-preview[bot] wants to merge 1 commit into
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Bumps [hw/deps/litex](https://github.com/enjoy-digital/litex) from `4f82a36` to `e0d5a7b`. - [Release notes](https://github.com/enjoy-digital/litex/releases) - [Commits](enjoy-digital/litex@4f82a36...e0d5a7b) Signed-off-by: dependabot-preview[bot] <support@dependabot.com>
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Bumps hw/deps/litex from
4f82a36toe0d5a7b.Commits
e0d5a7binterconnect/packet/Packetizer/Depacketizer: Avoid generating unaligned logic...0a919e7interconnect/packet: Improve PacketFIFO to handle payload/param separately.b2f8fa5gen/fhdl/verilog: Make DummyAttrTranslate a dict.bf52c10Merge pull request #969 from trabucayre/openfpgaloader_add_cable_and_freq_opt...730b57dbuild/gowin: Add initial timing constraints support.10ea45dbuild/microsemi/common: Cleanup MicrosemiPolarfireAsyncResetSynchronizerImpl.2b39325build: Simplify attr_translate (Now automatically defaults to None when not e...bdc3217gen/fhdl/verilog/_printattr: Avoid trying translating attribute when not supp...4fd974bbuild/gowin: Minor cleanups.3706ed7openfpgaloader.py: cast int to strDependabot will resolve any conflicts with this PR as long as you don't alter it yourself. You can also trigger a rebase manually by commenting
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