Core performance and size improvement#6

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Commits on Aug 30, 2020

Fixed dumb error in Adder logic
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Commits on Aug 31, 2020

Lot of signals renaming and 68k registers read/write improvement
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68k registers uses now two M4k memory blocks : new core size is 3200 LEs !!
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Commits on Sep 2, 2020

Created generic and Altera block RAM/ROM for registers and microcode
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