[gen] Change CSEL dependency instruction sequences

[ShaleXIONG]

To fix a problem that memory tag annotation combined with Csel such as T DpDataCseldW generates tests that triggered error Illegal operation readbit63 on x:green (User error) in herd7, we change the generated instruction sequences. In the new sequence, AArch64 CSEL dependency uses register self-compare instead of hardcode comparison against zero. This makes the selected CSEL path deterministic. It also removes the extra register instruction, e.g., diyone7 -arch AArch64 -variant memtag DpAddrCselsW Rfi -oneloc now generates:

`AArch64 CoRW1+addrcsels-rfi
Variant=memtag
Generator=diyone7 (version 7.58+1)
Com=Rf
Orig=DpAddrCselsW Rfi
"DpAddrCselsW Rfi"
{
 0:X0=x:green;
}
 P0                  ;
 LDR W1,[X0]         ;
 CMP W1,W1           ; (* previously MOV W3,#1  CMP W1, #0 *)
 CSEL W2,W3,W4,EQ    ; (* previously an extra clear-up AND W2,W2,#2  to set W2=0 *)
 MOV W5,#1           ;
 STR W5,[X0,W2,SXTW] ;

The similar sequence is also applied to DpDataCsel*. While for DpCtrlCsel*, for example diyone7 -arch AArch64 -variant memtag DpCtrlCselsW Rfi -oneloc, now generates:

AArch64 CoRW1+ctrlcsels-rfi
Variant=memtag
Generator=diyone7 (version 7.58+1)
Com=Rf
Orig=DpCtrlCselsW Rfi
"DpCtrlCselsW Rfi"
{
 0:X0=x:green;
}
 P0                ;
 LDR W1,[X0]       ;
 CMP W1,W1         ; (* previously CMP W1,#0 *)
 CSINC W2,W3,W4,EQ ; (* previous the false branch is W2 but now is a fresh register W4 *)
 CBNZ W2,LC00      ;
 LC00:             ;
 MOV W5,#1         ;
 STR W5,[X0]       ;

exists (0:X1=1)

This update is

Update the affected AArch64 generator baselines.