5-stage RV32I SystemVerilog pipeline (IF/ID/EX/MEM/WB) with stall/flush logic, hazard detection, full forwarding, and memory-mapped I/O. Achieved 110 MHz Fmax and ~0.7 IPC. Implemented ALU, decoder, branch/jump, and regfile. Verified via RISCOF and riscv-tests (>1K tests, 90% coverage).