SRAM ANALYSIS

[The project involved the design and analysis of a 6T SRAM memory cell using the LTspice development environment. Initially, the project focused on sizing the transistors associated with the memory cell and generating curves to calculate the noise margin during standby and read phases. Analysis included a graphical method to evaluate curve trends and calculate noise margin. The second phase implemented a method proposed in a specific article for noise margin analysis. This method utilized a new circuit configuration to directly calculate noise margin without graphical methods. The third phase involved Vdd scaling analysis to examine leakage power, hold, and read noise margin for varying supply voltages. Graphs were generated for each parameter to inform design considerations. Finally, the project analyzed the Data Retention Voltage parameter, obtaining a corresponding graph to inform design trade-offs adhering to specific constraints.]