Firmware: Move driver instances into driver implementation files

firmware/common/clock_gen.c

@@ -23,7 +23,6 @@
 
 #include <stdint.h>
 
-#include "drivers.h"
 #include "hackrf_ui.h"
 #include "i2c_bus.h"
 #include "platform_detect.h"
@@ -36,14 +35,14 @@
 
 void clock_gen_init(void)
 {
-	i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
+	i2c_bus_start(si5351c.bus, &i2c_config_si5351c_fast_clock);
 
-	si5351c_init(&clock_gen);
-	si5351c_disable_all_outputs(&clock_gen);
-	si5351c_disable_oeb_pin_control(&clock_gen);
-	si5351c_power_down_all_clocks(&clock_gen);
-	si5351c_set_crystal_configuration(&clock_gen);
-	si5351c_enable_xo_and_ms_fanout(&clock_gen);
+	si5351c_init(&si5351c);
+	si5351c_disable_all_outputs(&si5351c);
+	si5351c_disable_oeb_pin_control(&si5351c);
+	si5351c_power_down_all_clocks(&si5351c);
+	si5351c_set_crystal_configuration(&si5351c);
+	si5351c_enable_xo_and_ms_fanout(&si5351c);
 
 	/*
 	 * Clocks on HackRF One r9:
@@ -76,7 +75,7 @@ void clock_gen_init(void)
 	if (IS_H1_R9) {
 		/* MS0/CLK0 is the reference for both RFFC5071 and MAX2839. */
 		si5351c_configure_multisynth(
-			&clock_gen,
+			&si5351c,
 			0,
 			20 * 128 - 512,
 			0,
@@ -88,15 +87,15 @@ void clock_gen_init(void)
 	if (IS_NOT_H1_R9) {
 		/* MS4/CLK4 is the source for the RFFC5071 mixer (MAX2837 on rad1o). */
 		si5351c_configure_multisynth(
-			&clock_gen,
+			&si5351c,
 			4,
 			20 * 128 - 512,
 			0,
 			1,
 			0); /* 800/20 = 40MHz */
 		/* MS5/CLK5 is the source for the MAX2837 clock input (MAX2871 on rad1o). */
 		si5351c_configure_multisynth(
-			&clock_gen,
+			&si5351c,
 			5,
 			20 * 128 - 512,
 			0,
@@ -111,19 +110,19 @@ void clock_gen_init(void)
 	/* Set to 10 MHz, the common rate between Jawbreaker and HackRF One. */
 	sample_rate_set(SR_FP_MHZ(10), true);
 
-	si5351c_configure_clock_control(&clock_gen);
-	si5351c_set_clock_source(&clock_gen, PLL_SOURCE_XTAL);
+	si5351c_configure_clock_control(&si5351c);
+	si5351c_set_clock_source(&si5351c, PLL_SOURCE_XTAL);
 	// soft reset
-	si5351c_reset_pll(&clock_gen, SI5351C_PLL_BOTH);
-	si5351c_enable_clock_outputs(&clock_gen);
+	si5351c_reset_pll(&si5351c, SI5351C_PLL_BOTH);
+	si5351c_enable_clock_outputs(&si5351c);
 }
 
 void clock_gen_shutdown(void)
 {
-	i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
-	si5351c_disable_all_outputs(&clock_gen);
-	si5351c_disable_oeb_pin_control(&clock_gen);
-	si5351c_power_down_all_clocks(&clock_gen);
+	i2c_bus_start(si5351c.bus, &i2c_config_si5351c_fast_clock);
+	si5351c_disable_all_outputs(&si5351c);
+	si5351c_disable_oeb_pin_control(&si5351c);
+	si5351c_power_down_all_clocks(&si5351c);
 }
 
 clock_source_t activate_best_clock_source(void)
@@ -140,7 +139,7 @@ clock_source_t activate_best_clock_source(void)
 	clock_source_t source = CLOCK_SOURCE_HACKRF;
 
 	/* Check for external clock input. */
-	if (si5351c_clkin_signal_valid(&clock_gen)) {
+	if (si5351c_clkin_signal_valid(&si5351c)) {
 		source = CLOCK_SOURCE_EXTERNAL;
 	} else {
 #ifdef IS_EXPANSION_COMPATIBLE
@@ -149,7 +148,7 @@ clock_source_t activate_best_clock_source(void)
 			if (portapack_reference_oscillator && portapack()) {
 				portapack_reference_oscillator(true);
 				delay(510000); /* loop iterations @ 204MHz for >10ms for oscillator to enable. */
-				if (si5351c_clkin_signal_valid(&clock_gen)) {
+				if (si5351c_clkin_signal_valid(&si5351c)) {
 					source = CLOCK_SOURCE_PORTAPACK;
 				} else {
 					portapack_reference_oscillator(false);
@@ -161,7 +160,7 @@ clock_source_t activate_best_clock_source(void)
 	}
 
 	si5351c_set_clock_source(
-		&clock_gen,
+		&si5351c,
 		(source == CLOCK_SOURCE_HACKRF) ? PLL_SOURCE_XTAL : PLL_SOURCE_CLKIN);
 	hackrf_ui()->set_clock_source(source);
 
@@ -342,9 +341,9 @@ fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
 	if (IS_NOT_PRALINE) {
 		/* Integer mode can be enabled if p1 is even and p2 is zero. */
 		if (p1 & 0x1 || p2) {
-			si5351c_set_int_mode(&clock_gen, 0, 0);
+			si5351c_set_int_mode(&si5351c, 0, 0);
 		} else {
-			si5351c_set_int_mode(&clock_gen, 0, 1);
+			si5351c_set_int_mode(&si5351c, 0, 1);
 		}
 
 	#ifdef IS_H1_R9
@@ -353,7 +352,7 @@ fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
 			 * On HackRF One r9 all sample clocks are externally derived
 			 * from MS1/CLK1 operating at twice the sample rate.
 			 */
-			si5351c_configure_multisynth(&clock_gen, 1, p1, p2, p3, 0);
+			si5351c_configure_multisynth(&si5351c, 1, p1, p2, p3, 0);
 		}
 	#endif
 	#ifdef IS_NOT_H1_R9
@@ -363,11 +362,11 @@ fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
 			 * different sample clocks, all derived from multisynth 0.
 			 */
 			/* MS0/CLK0 is the source for the MAX5864/CPLD (CODEC_CLK). */
-			si5351c_configure_multisynth(&clock_gen, 0, p1, p2, p3, 1);
+			si5351c_configure_multisynth(&si5351c, 0, p1, p2, p3, 1);
 
 			/* MS0/CLK1 is the source for the CPLD (CODEC_X2_CLK). */
 			si5351c_configure_multisynth(
-				&clock_gen,
+				&si5351c,
 				1,
 				0,
 				0,
@@ -376,7 +375,7 @@ fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
 
 			/* MS0/CLK2 is the source for SGPIO (CODEC_X2_CLK) */
 			si5351c_configure_multisynth(
-				&clock_gen,
+				&si5351c,
 				2,
 				0,
 				0,
@@ -389,30 +388,30 @@ fp_28_36_t sample_rate_set(const fp_28_36_t sample_rate, const bool program)
 #ifdef IS_PRALINE
 	if (IS_PRALINE) {
 		/* MS0/CLK0 is the source for the MAX5864 (AFE_CLK). */
-		si5351c_configure_multisynth(&clock_gen, 0, p1, p2, p3, 1);
+		si5351c_configure_multisynth(&si5351c, 0, p1, p2, p3, 1);
 
 		/* MS1/CLK1 is the source for the FPGA (FPGA_CLK and SCT_CLK). */
-		si5351c_configure_multisynth(&clock_gen, 1, p1, p2, p3, 1);
+		si5351c_configure_multisynth(&si5351c, 1, p1, p2, p3, 1);
 
 		/* Delay FPGA_CLK relative to AFE_CLK. */
 		uint8_t phase_offset = 0;
 		if (p1 < 2100) {
 			phase_offset = (p1 >> 4) - 6;
 		}
-		si5351c_set_phase(&clock_gen, 1, phase_offset);
+		si5351c_set_phase(&si5351c, 1, phase_offset);
 
 		if ((detected_revision() & ~BOARD_REV_GSG) < BOARD_REV_PRALINE_R1_1) {
 			/*
 			 * On older boards FPGA_CLK is on CLK2 while SCT_CLK is on
 			 * CLK1. We configure both so that behavior is consistent with
 			 * newer boards that use CLK1 for both FPGA_CLK and SCT_CLK.
 			 */
-			si5351c_configure_multisynth(&clock_gen, 2, p1, p2, p3, 1);
-			si5351c_set_phase(&clock_gen, 2, phase_offset);
+			si5351c_configure_multisynth(&si5351c, 2, p1, p2, p3, 1);
+			si5351c_set_phase(&si5351c, 2, phase_offset);
 		}
 
 		/* Reset PLL to synchronize output clock phase. */
-		si5351c_reset_pll(&clock_gen, SI5351C_PLL_A);
+		si5351c_reset_pll(&si5351c, SI5351C_PLL_A);
 	}
 #endif
 

firmware/common/clock_io.c

@@ -30,9 +30,11 @@
 #include <libopencm3/lpc43xx/gpdma.h>
 #include <libopencm3/lpc43xx/creg.h>
 
-#include "drivers.h"
 #include "gpdma.h"
 #include "gpio.h"
+#ifdef IS_NOT_PRALINE
+	#include "sgpio.h"
+#endif
 #ifdef IS_PRALINE
 	#include "fpga.h"
 	#include "platform_gpio.h"

firmware/common/cpld_jtag.c

@@ -34,6 +34,13 @@ static uint32_t xsvf_buffer_len, xsvf_pos;
 static unsigned char* xsvf_buffer;
 #endif
 
+/* Driver instance. */
+jtag_gpio_t jtag_gpio_cpld = {};
+
+jtag_t jtag_cpld = {
+	.gpio = &jtag_gpio_cpld,
+};
+
 void cpld_jtag_take(jtag_t* const jtag)
 {
 	const jtag_gpio_t* const gpio = jtag->gpio;

firmware/common/cpld_jtag.h

@@ -59,3 +59,7 @@ int cpld_jtag_program(
 	unsigned char* const buffer,
 	refill_buffer_cb refill);
 unsigned char cpld_jtag_get_next_byte(void);
+
+/* Driver instance. */
+extern jtag_gpio_t jtag_gpio_cpld;
+extern jtag_t jtag_cpld;

firmware/common/cpu_clock.c

@@ -29,8 +29,8 @@
 #endif
 
 #include "delay.h"
-#include "drivers.h"
 #include "i2c_bus.h"
+#include "si5351c.h"
 #ifdef IS_NOT_RAD1O
 	#include "platform_detect.h"
 #endif
@@ -116,7 +116,7 @@ void cpu_clock_init(void)
 
 	//FIXME disable I2C
 	/* Kick I2C0 down to 400kHz when we switch over to APB1 clock = 204MHz */
-	i2c_bus_start(clock_gen.bus, &i2c_config_si5351c_fast_clock);
+	i2c_bus_start(si5351c.bus, &i2c_config_si5351c_fast_clock);
 
 	/*
 	 * 12MHz clock is entering LPC XTAL1/OSC input now.

firmware/common/da7219.c

@@ -22,7 +22,6 @@
 #include <stdint.h>
 
 #include "da7219.h"
-#include "drivers.h"
 #include "i2c_bus.h"
 
 #define DA7219_REG_CHIP_ID1 0x81