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Add multisymbol RLE implementation #1052

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c9d8272
[RLE] Support multiple symbols/pairs in single transaction
mtdudek Jul 20, 2023
13e09b9
[DSLX] Add advanced RunLengthEncoder
mtdudek Jun 29, 2023
ccb35f7
[RLE]: Improve high level overview on Multisymbol encoder
mtdudek Jul 31, 2023
f16f00e
xls:modules:rle: Review: update comments
mtdudek Aug 28, 2023
a84a8ec
xls:modules:rle: Add description for Multisymbol RLE
mtdudek Aug 29, 2023
66ff962
xls:modules:rle: Review: Change step to proc
mtdudek Aug 31, 2023
d28d81b
review: Update adv rle enc documentation
mtdudek Oct 6, 2023
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209 changes: 209 additions & 0 deletions xls/modules/rle/BUILD
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Original file line number Diff line number Diff line change
Expand Up @@ -106,6 +106,215 @@ xls_benchmark_ir(
},
)

xls_dslx_library(
name = "rle_enc_adv_reduce_stage_dslx",
srcs = [
"rle_enc_adv_reduce_stage.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_reduce_stage_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_reduce_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_reduce_stage_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_reduce_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_reduce_stage_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_reduce_stage_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_realign_stage_dslx",
srcs = [
"rle_enc_adv_realign_stage.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_realign_stage_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_realign_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_realign_stage_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_realign_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_realign_stage_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_realign_stage_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_core_dslx",
srcs = [
"rle_enc_adv_core.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_core_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_core_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_core_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_core_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_core_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_core_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_adjust_width_stage_dslx",
srcs = [
"rle_enc_adv_adjust_width_stage.x",
],
deps = [
":rle_common_dslx"
],
)

xls_dslx_test(
name = "rle_enc_adv_adjust_width_stage_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_adjust_width_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_adjust_width_stage_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_adjust_width_stage_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_adjust_width_stage_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_adjust_width_stage_dslx",
)

xls_dslx_library(
name = "rle_enc_adv_dslx",
srcs = [
"rle_enc_adv.x",
],
deps = [
":rle_common_dslx",
":rle_enc_adv_reduce_stage_dslx",
":rle_enc_adv_realign_stage_dslx",
":rle_enc_adv_core_dslx",
":rle_enc_adv_adjust_width_stage_dslx",
],
)

xls_dslx_test(
name = "rle_enc_adv_dslx_test",
dslx_test_args = {
"compare": "none",
},
library = "rle_enc_adv_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_dslx_ir_test",
dslx_test_args = {
"compare": "interpreter",
},
library = "rle_enc_adv_dslx",
)

xls_dslx_test(
name = "rle_enc_adv_dslx_jit_test",
dslx_test_args = {
"compare": "jit",
},
library = "rle_enc_adv_dslx",
)

xls_dslx_ir(
name = "rle_enc_adv_ir",
dslx_top = "RunLengthEncoder8_8_4_2",
library = "rle_enc_adv_dslx",
ir_file = "rle_enc_adv.ir",
)

xls_ir_opt_ir(
name = "rle_enc_adv_opt_ir",
src = "rle_enc_adv.ir",
top = "__xls_modules_rle_rle_enc_adv_core__RunLengthEncoder8_8_4_2__RunLengthEncoderAdvanced__RunLengthEncoderAdvancedCoreStage_0__8_4_8_next",
)

xls_ir_verilog(
name = "rle_enc_adv_verilog",
src = ":rle_enc_adv_opt_ir.opt.ir",
verilog_file = "rle_enc_adv.v",
codegen_args = {
"module_name": "rle_enc_adv",
"delay_model": "unit",
"pipeline_stages": "2",
"reset": "rst",
"use_system_verilog": "false",
},
)

xls_benchmark_ir(
name = "rle_enc_adv_ir_benchmark",
src = ":rle_enc_adv_opt_ir.opt.ir",
benchmark_ir_args = {
"pipeline_stages": "2",
"delay_model": "unit",
}
)

xls_dslx_library(
name = "rle_dec_dslx",
srcs = [
Expand Down
15 changes: 8 additions & 7 deletions xls/modules/rle/rle_common.x
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Original file line number Diff line number Diff line change
Expand Up @@ -19,16 +19,17 @@
// Structure is used as an input and an output to and from
// a preprocessing stage as well as an input to a RLE encoder.
// It is also used as an output from RLE decoder.
pub struct PlainData<SYMB_WIDTH: u32> {
symbol: bits[SYMB_WIDTH], // symbol
last: bool, // flush RLE
pub struct PlainData<SYMB_WIDTH: u32, SYMB_COUNT: u32> {
symbols: bits[SYMB_WIDTH][SYMB_COUNT], // symbols
symbol_valids: bits[1][SYMB_COUNT], // symbol valid
last: bool, // flush RLE
}

// Structure contains compressed (symbol, counter) pairs.
// Structure is used as an output from RLE encoder and
// as an input to RLE decoder.
pub struct CompressedData<SYMBOL_WIDTH: u32, COUNT_WIDTH: u32> {
symbol: bits[SYMBOL_WIDTH], // symbol
count: bits[COUNT_WIDTH], // symbol counter
last: bool, // flush RLE
pub struct CompressedData<SYMBOL_WIDTH: u32, COUNT_WIDTH: u32, PAIR_COUNT: u32> {
symbols: bits[SYMBOL_WIDTH][PAIR_COUNT], // symbol
counts: bits[COUNT_WIDTH][PAIR_COUNT], // symbol counter
last: bool, // flush RLE
}
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