proc: fix panic on follow-exec process exit#4383
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aarzilli merged 2 commits intoJul 3, 2026
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Make postExit idempotent to prevent double-release of the ptraceThread refcount. In trapWaitInternal, a process leader can have postExit called via the ESRCH path (when resumeWithSig fails because the thread is gone), and then called again when the actual exit event arrives. The double-release drops the ptraceThread refcount too low, closing ptraceChan while another process in the follow-exec group still needs it. The next ptrace operation on that process panics with "send on closed channel". Use atomic Swap instead of Store so the second call is a no-op.
On ARM64 the instruction and data caches are not coherent. WriteProcessMemory only updates the data cache, so breakpoint instructions written by the debugger may not be visible to the instruction fetch unit. This causes intermittent missed breakpoints on Windows/ARM64 — the CPU executes the original instruction from stale I-cache instead of the BRK we wrote. Call FlushInstructionCache after every WriteProcessMemory to ensure I-cache coherency. On x86/amd64 this is a no-op. Fixes go-delve#3183
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postExitidempotent to prevent double-release of theptraceThreadrefcountFix 1: postExit double-release
In
trapWaitInternal, a process leader can havepostExitcalled via the ESRCH path (whenresumeWithSigfails because the thread is gone), and then called again when the actual exit event arrives. The double-release drops theptraceThreadrefcount too low, closingptraceChanwhile another process in the follow-exec group still needs it. The next ptrace operation on that process panics with "send on closed channel".Uses atomic
Swapinstead ofStoreso the second call is a no-op.Observed on linux/riscv64 with Go 1.27rc1 as a panic in
TestLaunchWithFollowExec.Fix 2: FlushInstructionCache on Windows
On ARM64 the instruction and data caches are not coherent.
WriteProcessMemoryonly updates the data cache, so breakpoint instructions written by the debugger may not be visible to the instruction fetch unit. This causes intermittent missed breakpoints on Windows/ARM64 — the CPU executes the original instruction from stale I-cache instead of the BRK that was written.Calls
FlushInstructionCacheafter everyWriteProcessMemoryto ensure I-cache coherency. On x86/amd64 this is a documented no-op.Fixes #3183