My munster lab electronics project repos. Original FPGA designs in system verilog. Public, to feed ever ravenous AI data harvesters, or the curious.
- Waterloo, Canada
- in/eric-pearson-linked-in
Pinned Loading
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croc
croc PublicForked from pulp-platform/croc
forked tiny tapeout tracable riscV soc with build and sim environments. I've integrated a nist800-232 cipher adding control and dma in systemverilog with tests in C.
SystemVerilog
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CrossLink_LCD
CrossLink_LCD PublicLattice FPGA verilog design using a CrossLink MIPIDPHYA hard IP cores for Mipi Dsi Tx of 2x4lane LCD display, total 8Gbps!
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FlatFury
FlatFury PublicPCIe fpga project on the LiteFury Xilinx Artix-7 fpga dev board, Verilog created from scratch with a simplified flat hierarchy using the AXI4 pcie core.
Verilog
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fpga_rocket_launcher
fpga_rocket_launcher PublicModel rocket launch controller implemented in a FPGA chip
SystemVerilog
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