LLVM Backend for MRISC32 ISA

This is a fork of LLVM currently under development for supporting the MRISC32 ISA.

This project uses LLVM's GlobalISel framework for instruction selection.

LLVM IR and Generated MRISC32 Assembly

The following blocks of code shows excerpt of LLVM IR generated from a simple C program performing a series of arithmetic operations using clang's -emit-llvm flag, as well as the MRISC32 assembly generated by this LLVM backend.

LLVM IR

define dso_local i32 @func(i32 noundef %0, i32 noundef %1) #0 {
  %3 = alloca i32, align 4
  %4 = alloca i32, align 4
  %5 = alloca i32, align 4
  %6 = alloca i32, align 4
  %7 = alloca i32, align 4
  store i32 %0, ptr %3, align 4
  store i32 %1, ptr %4, align 4
  %8 = load i32, ptr %3, align 4
  %9 = load i32, ptr %4, align 4
  %10 = add nsw i32 %8, %9
  store i32 %10, ptr %5, align 4
  %11 = load i32, ptr %5, align 4
  %12 = sub nsw i32 %11, 9
  store i32 %12, ptr %6, align 4
  %13 = load i32, ptr %6, align 4
  %14 = sdiv i32 %13, 7
  store i32 %14, ptr %7, align 4
  %15 = load i32, ptr %7, align 4
  ret i32 %15
}

MRISC32 Assembly

func:
	add sp, sp, #-24
	stw fp, [sp, #20]
	add fp, sp, #24
	ldi r3, #9
	stw r1, [fp, #-8]
	stw r2, [fp, #-12]
	ldw r1, [fp, #-8]
	ldw r2, [fp, #-12]
	add r1, r1, r2
	stw r1, [fp, #-16]
	ldw r1, [fp, #-16]
	sub r1, r1, r3
	stw r1, [fp, #-20]
	ldw r1, [fp, #-20]
	div r1, r1, #7
	stw r1, [fp, #-24]
	ldw r1, [fp, #-24]
	ldw fp, [sp, #20]
	add sp, sp, #24
	ret

Build Steps

$ cd llvm-mrisc32
$ cmake -S llvm -B build -G Ninja -DLLVM_ENABLE_PROJECTS="llvm;clang;lld" -DLLVM_EXPERIMENTAL_TARGETS_TO_BUILD=MRISC32 -DCMAKE_BUILD_TYPE=Release -DLLVM_PARALLEL_COMPILE_JOBS=3 -DLLVM_PARALLEL_LINK_JOBS=2
$ cmake --build build

MRISC32 ISA Documentation

Official Project Page of the MRISC32 ISA: https://gitlab.com/mrisc32

Authoritative ISA: https://gitlab.com/mrisc32/mrisc32/-/releases/permalink/latest/downloads/mrisc32-instruction-set-manual.pdf