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What are the changes to be made to map two compute units ?

Status: Open.

#14 In dicecco1/fpga_caffe;

· aeeshms opened on Jul 13, 2018

Questions about optimal parameters

Status: Open.

#13 In dicecco1/fpga_caffe;

· YaoYuxin opened on Jun 5, 2018

Extending this framework with Intel Arria 10 in future?

Status: Open.

#12 In dicecco1/fpga_caffe;

· manojrohit opened on Apr 26, 2018

Error when training LeNet

Status: Open.

#11 In dicecco1/fpga_caffe;

· jingxianx opened on Mar 17, 2018

about alexnet

Status: Open.

#6 In dicecco1/fpga_caffe;

· OverDriveMC opened on Nov 20, 2017

no winograd_pe.cl file

Status: Open.

#4 In dicecco1/fpga_caffe;

· haisenbao opened on Aug 21, 2017

make runtest failing

Status: Open.

#3 In dicecco1/fpga_caffe;

· sammhho opened on Aug 5, 2017