third_party/hal_sifli/sf32lb52: mark kernel RAM non-cacheable#1549
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jplexer wants to merge 1 commit into
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third_party/hal_sifli/sf32lb52: mark kernel RAM non-cacheable#1549jplexer wants to merge 1 commit into
jplexer wants to merge 1 commit into
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Fixes FIRM-2513 Signed-off-by: Joshua Jun <lets@throw.rocks>
gmarull
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Jun 17, 2026
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this needs better explanation. why cache invd ops can't be used?
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We have some hardfaults that are in the SiFli HAL's DMA descriptor state, not our buffers, so cache ops mean clean/invalidate inside vendor code on every DMA path, all 32B-aligned. Already tried targeted flushes (4bde4ee/3ff6d0d06), but issue still persists. Non-cacheable kernel RAM just kills the whole problem, practically free (D-cache still covers XIP flash), and it's the known-good state from before we enabled MPU. |
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@jplexer pls share some more problem details with @rabbitsaviola |
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Fixes FIRM-2513