LST: set T5 occupancy threshold at 100K#51333
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cms-bot internal usage |
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+code-checks Logs: https://cmssdt.cern.ch/SDT/code-checks/cms-sw-PR-51333/49964 |
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A new Pull Request was created by @slava77 for master. It involves the following packages:
@Moanwar, @cmsbuild, @jfernan2, @mandrenguyen, @srimanob can you please review it and eventually sign? Thanks. cms-bot commands are listed here |
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@slava77 thanks for looking into this in such a short time. |
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test parameters:
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@cmsbuild, please test |
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CPU; I updated the PR description |
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the timing tests failures look related to some kind of glitch the bot |
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-1 Failed Tests: HLTP2Timing RelVals-AMD_MI300X Failed RelVals-AMD_MI300X
Comparison SummarySummary:
NVIDIA_H100 Comparison SummarySummary:
NVIDIA_L40S Comparison SummarySummary:
NVIDIA_T4 Comparison SummarySummary:
Max Memory Comparisons exceeding threshold NVIDIA_H100@cms-sw/core-l2 , I found 1 workflow step(s) with memory usage exceeding the error threshold: Expand to see workflows ...
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For the sake of completeness of the record, the relevant bits of the stack trace are below. Threads 6 and 7 are in Sitting on a lock in Edited stack trace: |
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This is an interim measure to address the very extreme tail event(s) such as seen the phase-2 170pre2 relval QCD 2TeV jet events in #51245 (comment)
a somewhat rounded upper limit of 100K is placed on the maximum number of T5s (per module [accounting unit]).
The slow event seen in the relval (tarball used to reproduce)
Tests on 1K events show minimal differences in physics (tracking running on GPU, some non-reproducibility expected)
(all HLT MTV plots for QCD and ttbar)