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You might have encountered building cache issues. You might get a clean environment, delete the printf and build the emulator again.
The snippet you show is exactly the way to add printf, and it will become effective by |
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Type of issue: Question
Problem Description
I am a newbie to Rocketchip and I have been using Verilator to develop some custom features on Rocketchip. During my development process, I usually rely on waveform debugging to identify bugs. However, I have encountered a problem that only occurs when the emulator is not in debug mode. Unfortunately, generating waveforms is only possible when the emulator is compiled in debug mode.
To address this bug, I would like to know if there is a way to add print statements in Rocketchip's Chisel code.
What I have tried
I have tried to add printf in CSR.scala directly but no luck. I have also noticed that there are some existing printf statements in RocketCore.scala which look like:
It seems that output of the executed assembly tests under emulator/output/*.out is generated here. However when I delete these print statements, those logs can still be generated. This makes me unsure if the printf in Rocketore.scala is actually working.
Command I use
Environment
Thanks for your attention to this matter. Any reply will be highly appreciated.
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