Type of issue: Question
Problem Description
I am a newbie to Rocketchip and I have been using Verilator to develop some custom features on Rocketchip. During my development process, I usually rely on waveform debugging to identify bugs. However, I have encountered a problem that only occurs when the emulator is not in debug mode. Unfortunately, generating waveforms is only possible when the emulator is compiled in debug mode.
To address this bug, I would like to know if there is a way to add print statements in Rocketchip's Chisel code.
What I have tried
I have tried to add printf in CSR.scala directly but no luck. I have also noticed that there are some existing printf statements in RocketCore.scala which look like:
printf("C%d: %d [%d] pc=[%x] W[r%d=%x][%d] R[r%d=%x] R[r%d=%x] inst=[%x] DASM(%x)\n",
io.hartid, coreMonitorBundle.timer, coreMonitorBundle.valid,
coreMonitorBundle.pc,
Mux(wb_ctrl.wxd || wb_ctrl.wfd, coreMonitorBundle.wrdst, 0.U),
Mux(coreMonitorBundle.wrenx, coreMonitorBundle.wrdata, 0.U),
coreMonitorBundle.wrenx,
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0src, 0.U),
Mux(wb_ctrl.rxs1 || wb_ctrl.rfs1, coreMonitorBundle.rd0val, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1src, 0.U),
Mux(wb_ctrl.rxs2 || wb_ctrl.rfs2, coreMonitorBundle.rd1val, 0.U),
coreMonitorBundle.inst, coreMonitorBundle.inst)
}
It seems that output of the executed assembly tests under emulator/output/*.out is generated here. However when I delete these print statements, those logs can still be generated. This makes me unsure if the printf in Rocketore.scala is actually working.
Command I use
./emulator-freechips.rocketchip.system-freechips.rocketchip.system.DefaultConfig +max-cycles=100000000 +verbose output/cvm.riscv 3>&1 1>&2 2>&3 | /opt/riscv/bin/spike-dasm > output/cvm.riscv.out
Environment
RocketChip Commit: 25e2c63567689ebe1fc5e60fdfe3375a8dba071c
Host Linux version: 5.19.0-45-generic #46~22.04.1-Ubuntu SMP PREEMPT_DYNAMIC Wed Jun 7 15:06:04 UTC 20 x86_64 x86_64 x86_64 GNU/Linux
sbt version: 1.8.3
Thanks for your attention to this matter. Any reply will be highly appreciated.
Type of issue: Question
Problem Description
I am a newbie to Rocketchip and I have been using Verilator to develop some custom features on Rocketchip. During my development process, I usually rely on waveform debugging to identify bugs. However, I have encountered a problem that only occurs when the emulator is not in debug mode. Unfortunately, generating waveforms is only possible when the emulator is compiled in debug mode.
To address this bug, I would like to know if there is a way to add print statements in Rocketchip's Chisel code.
What I have tried
I have tried to add printf in CSR.scala directly but no luck. I have also noticed that there are some existing printf statements in RocketCore.scala which look like:
It seems that output of the executed assembly tests under emulator/output/*.out is generated here. However when I delete these print statements, those logs can still be generated. This makes me unsure if the printf in Rocketore.scala is actually working.
Command I use
Environment
Thanks for your attention to this matter. Any reply will be highly appreciated.