Fix CIC interpolator and add model/tests#1
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The comb and integrator instantiations used positional parameters and wrong port names that don't match their module definitions. Use named parameters/ports and a uniform ACC_DW width for all internal stages. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Add cic_i_model.py that models the RTL cic_i.sv behavior:
- Comb stages all fire simultaneously on in_dv (matching RTL wiring)
- Integrator accumulators use modular arithmetic (ACC_DW-bit wrapping)
- Output truncation matches RTL bit-select: int_out[ACC_DW-1 -: OUT_DW]
Add test_cic_i.py with parametrized cocotb tests covering:
- r ∈ {4, 10}, m ∈ {3, 6}, g ∈ {1, 2}, dw ∈ {8, 16} (16 combinations)
Minor: remove trailing semicolon in cic_d_model.py.
Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
Standalone script that feeds a 5 kHz sine (20 kHz sample rate) through the CIC interpolator model with R=4, plotting input and output spectra for N=1..5 to visualize image suppression vs CIC order. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
catkira
changed the title
The test code uses cocotb 1.x APIs (cocotb.fork, Task.kill). Pin cocotb<2 in requirements.txt so CI installs a compatible version. Co-Authored-By: Claude Opus 4.6 <noreply@anthropic.com>
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catkira
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Feb 23, 2026
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Summary
model/cic_i_model.py)tests/test_cic_i.py) parameterized over R, N, M, and data widthtests/spectral_analysis_cic_i.py) that visualizes image suppression vs CIC order (N=1..5) for a 5 kHz sine interpolated from 20 kHz to 80 kHz (R=4)Test plan
pytest tests/test_cic_d.py— 88 tests, 3 min)pytest tests/test_cic_i.pyto verify RTL matches Python model across parameter combinationspython tests/spectral_analysis_cic_i.pyto verify spectral plots show increasing image suppression with higher N🤖 Generated with Claude Code