[pull] Implement verilog with bad formatting

[mczyz-antmicro]

No description provided.

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	module hello(
	input clk);
	module hello (
	input clk
	);

[github-actions]

[verible-verilog-format] _{reported by reviewdog 🐶}

Suggested change

	initial
	begin: proc_disp_hi
	$display("Hello");
	end
	initial begin : proc_disp_hi
	$display("Hello");
	end