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Added patches for the ROSELINE project #2

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Added patches for the ROSELINE project #2

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f83e9ec
Added some patches to enable socket timestamping over ieee802154 inte…
asymingt Sep 29, 2015
5a3c23e
Added the ROSELINE kernel defconfig
asymingt Sep 29, 2015
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7 changes: 0 additions & 7 deletions arch/arm/boot/dts/am335x-bone-common.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,6 @@

&am33xx_pinmux {
pinctrl-names = "default";
pinctrl-0 = <&clkout2_pin>;

user_leds_s0: user_leds_s0 {
pinctrl-single,pins = <
Expand Down Expand Up @@ -95,12 +94,6 @@
>;
};

clkout2_pin: pinmux_clkout2_pin {
pinctrl-single,pins = <
0x1b4 (PIN_OUTPUT_PULLDOWN | MUX_MODE3) /* xdma_event_intr1.clkout2 */
>;
};

cpsw_default: cpsw_default {
pinctrl-single,pins = <
/* Slave 1 */
Expand Down
195 changes: 159 additions & 36 deletions arch/arm/boot/dts/am335x-boneblack.dts
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Original file line number Diff line number Diff line change
Expand Up @@ -34,53 +34,176 @@
};

&am33xx_pinmux {
nxp_hdmi_bonelt_pins: nxp_hdmi_bonelt_pins {
pinctrl-single,pins = <
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */
0xa0 0x08 /* lcd_data0.lcd_data0, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xa4 0x08 /* lcd_data1.lcd_data1, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xa8 0x08 /* lcd_data2.lcd_data2, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xac 0x08 /* lcd_data3.lcd_data3, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb0 0x08 /* lcd_data4.lcd_data4, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb4 0x08 /* lcd_data5.lcd_data5, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xb8 0x08 /* lcd_data6.lcd_data6, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xbc 0x08 /* lcd_data7.lcd_data7, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc0 0x08 /* lcd_data8.lcd_data8, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc4 0x08 /* lcd_data9.lcd_data9, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xc8 0x08 /* lcd_data10.lcd_data10, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xcc 0x08 /* lcd_data11.lcd_data11, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd0 0x08 /* lcd_data12.lcd_data12, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd4 0x08 /* lcd_data13.lcd_data13, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xd8 0x08 /* lcd_data14.lcd_data14, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xdc 0x08 /* lcd_data15.lcd_data15, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT | AM33XX_PULL_DISA */
0xe0 0x00 /* lcd_vsync.lcd_vsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xe4 0x00 /* lcd_hsync.lcd_hsync, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xe8 0x00 /* lcd_pclk.lcd_pclk, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
0xec 0x00 /* lcd_ac_bias_en.lcd_ac_bias_en, OMAP_MUX_MODE0 | AM33XX_PIN_OUTPUT */
>;

/* For a uart device */
uart5_pins: pinmux_uart5_pins {
pinctrl-single,pins = <
0xC4 0x24 /* P8.38 uart5_rxd MODE6 INPUT (RX) */
0xC0 0x04 /* P8.37 uart5_txd MODE6 OUTPUT (TX) */
>;
};

/* For SPI0 device */
spi0_pins_s0: spi0_pins_s0 {
pinctrl-single,pins = <
0x040 0x17 /* SLPTR P9.15 O_PULLUP | MODE7-GPIO1[16] */
0x04c 0x17 /* RSTN P9.16 O_PULLUP | MODE7-GPIO1[19] */
0x1a4 0x37 /* IRQ P9.27 I_PULLUP | MODE7-GPIO3[19] */
0x150 0x30 /* CLK P9.22 spi0_sclk, I_PULLUP | MODE0 */
0x154 0x10 /* D0 P9.21 MOSI spi0_d0, O_PULLUP | MODE0 */
0x158 0x30 /* D1 P9.18 MISO spi0_d1, I_PULLUP | MODE0 */
0x15c 0x10 /* SS P9.17 spi0_cs0, O_PULLUP | MODE0 */
>;
};
nxp_hdmi_bonelt_off_pins: nxp_hdmi_bonelt_off_pins {
pinctrl-single,pins = <
0x1b0 0x03 /* xdma_event_intr0, OMAP_MUX_MODE3 | AM33XX_PIN_OUTPUT */

/* For SPI1 device */
spi1_pins_s0: spi1_pins_s0 {
pinctrl-single,pins = <
0x038 0x17 /* RESET P8.16 O_PULLUP | MODE7-GPIO1[14] */
0x03c 0x37 /* IRQ P8.15 I_PULLUP | MODE7-GPIO1[15] */
0x190 0x33 /* P9.31 CLK INPUT_PULLUP | MODE3 */
0x194 0x33 /* P9.29 MISO INPUT_PULLUP | MODE3 */
0x198 0x13 /* P9.30 MOSI OUTPUT_PULLUP | MODE3 */
0x19c 0x13 /* P9.28 CS0 OUTPUT_PULLUP | MODE3 */
>;
};

/* For an i2c device */
bb_i2c2_pins: pinmux_bb_i2c2_pins {
pinctrl-single,pins = <
0x178 0x73 /* I2C2_SDA, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
0x17c 0x73 /* I2C2_SCL, SLEWCTRL_SLOW | INPUT_PULLUP | MODE3 */
>;
};

/* Timer configuration */
timer_pins: pinmux_timer_pins {
pinctrl-single,pins = <
0x90 0x22 /* P8.7 MODE2 TIMER4 - 24MHz CAPTURE */
0x98 0x02 /* P8.10 MODE2 TIMER5 - 24MHz INTERRUPT */
0x9C 0x22 /* P8.9 MODE2 TIMER6 - TCLKIN CAPTURE */
0x94 0x02 /* P8.8 MODE2 TIMER7 - TCLKIN INTERRUPT */
0x1b4 0x2A /* P9.41A MODE2 TIMER4 TCLKIN */
0x1a8 0x0F /* P9.41B MODE7 TIMER4 INPUT (high-Z, tied to P9.41A) - conflicts with HDMI */
>;
};

/* PWMSS configuration */
epwmss1_pins: pinmux_epwmss1_pins {
pinctrl-single,pins = <
0x0c8 0x02 /* P8_36 = EHRPWM1A, MODE2 */
0x0cc 0x02 /* P8_34 = EHRPWM1B, MODE2 */
0x0D8 0x22 /* P8_31 = GPIO0_10 = EQEP1_index, MODE2 */
0x0DC 0x22 /* P8_32 = GPIO0_11 = EQEP1_strobe, MODE2 */
0x0D4 0x32 /* P8_33 = GPIO0_9 = EQEP1B_in, MODE2 */
0x0D0 0x32 /* P8_35 = GPIO0_8 = EQEP1A_in, MODE2 */
>;
};
epwmss2_pins: pinmux_epwmss2_pins {
pinctrl-single,pins = <
0x024 0x04 /* P8_13 = EHRPWM2A, MODE4 */
0x020 0x04 /* P8_19 = EHRPWM2A, MODE4 */
0x0B8 0x23 /* P8_39 = GPIO2_12 = EQEP2_index, MODE3 */
0x0BC 0x23 /* P8_40 = GPIO2_13 = EQEP2_strobe, MODE3 */
0x0B0 0x33 /* P8_41 = GPIO2_10 = EQEP2A_in, MODE3 */
0x0B4 0x33 /* P8_42 = GPIO2_11 = EQEP2B_in, MODE3 */
>;
};
};

&lcdc {
status = "okay";
};

/ {
hdmi {
compatible = "ti,tilcdc,slave";
i2c = <&i2c0>;
pinctrl-names = "default", "off";
pinctrl-0 = <&nxp_hdmi_bonelt_pins>;
pinctrl-1 = <&nxp_hdmi_bonelt_off_pins>;
&rtc {
system-power-controller;
};

&uart5 {
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&uart5_pins>;
};

&epwmss1 {
status = "okay";
pinctrl-0 = <&epwmss1_pins>;
ehrpwm1: ehrpwm@48302200 {
#pwm-cells = <3>;
compatible = "ti,am33xx-ehrpwm";
reg = <0x48302200 0x80>;
ti,hwmods = "ehrpwm1";
status = "okay";
};
eqep1: eqep@0x48302180 {
compatible = "ti,am33xx-eqep";
reg = <0x48302180 0x80>;
interrupt-parent = <&intc>;
interrupts = <88>;
ti,hwmods = "eqep1";
status = "okay";
};
};

&rtc {
system-power-controller;
&epwmss2 {
status = "okay";
pinctrl-0 = <&epwmss2_pins>;
ehrpwm2: ehrpwm@48304200 {
#pwm-cells = <3>;
compatible = "ti,am33xx-ehrpwm";
reg = <0x48304200 0x80>;
ti,hwmods = "ehrpwm2";
status = "okay";
};
eqep2: eqep@0x48304180 {
compatible = "ti,am33xx-eqep";
reg = <0x48304180 0x80>;
interrupt-parent = <&intc>;
interrupts = <89>;
ti,hwmods = "eqep2";
status = "okay";
};
};

&spi0 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi0_pins_s0>;
ti,pindir-d0-out-d1-in = <1>;
at86rf233@0 {
spi-max-frequency = <7500000>;
reg = <0>;
compatible = "atmel,at86rf233";
interrupts = <19 1>;
interrupt-parent = <&gpio3>;
reset-gpio = <&gpio1 19 0>;
sleep-gpio = <&gpio1 16 0>;
};
};

&spi1 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&spi1_pins_s0>;
dw1000@1 {
spi-max-frequency = <10000000>;
reg = <0>;
compatible = "decawave,dw1000";
interrupts = <15 2>;
interrupt-parent = <&gpio1>;
reset-gpio = <&gpio1 14 0>;
};
};

&i2c2 {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
pinctrl-names = "default";
pinctrl-0 = <&bb_i2c2_pins>;
clock-frequency = <100000>;
};
2 changes: 1 addition & 1 deletion arch/arm/boot/dts/am33xx-clocks.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -160,7 +160,7 @@
tclkin_ck: tclkin_ck {
#clock-cells = <0>;
compatible = "fixed-clock";
clock-frequency = <12000000>;
clock-frequency = <16000000>;
};

dpll_core_ck: dpll_core_ck {
Expand Down
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