Fix signed overflow in SA-1 clock frequency calculation#4
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When the loop counter exceeds 32767, the hardware multiplier treats it as signed negative. Correct for this by conditionally adding the constant multipler to the upper 16 bits of the result (the loop counter is added unconditionally since the constant multiplier is always "signed negative") Also fix the subsequent division: halve the dividend before division so it stays out of signed negative territory, then double the quotient and remainder of the result and adjust for odd dividends and "modulo overflow" (remainder >= quotient). This allows the test to actually show frequencies between ~29 and ~59MHz. Before it would wrap to ~3MHz and scale strangely.
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(feel free to cut down on the comments inside the code; I chose verbosity partly to explain to myself what was happening 😅) |
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When the loop counter exceeds 32767, the hardware multiplier treats it as signed negative. Correct for this by conditionally adding the constant multipler to the upper 16 bits of the result (the loop counter is added unconditionally since the constant multiplier is always "signed negative")
Also fix the subsequent division: halve the dividend before division so it stays out of signed negative territory, then double the quotient and remainder of the result and adjust for odd dividends and "modulo overflow" (remainder >= quotient).
This allows the test to actually show frequencies between ~29 and ~59MHz. Before it would wrap to ~3MHz and scale strangely.