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Improve hierarchy#857

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DRubioG wants to merge 5 commits into
TerosTechnology:devfrom
DRubioG:improve_hierarchy
Open

Improve hierarchy#857
DRubioG wants to merge 5 commits into
TerosTechnology:devfrom
DRubioG:improve_hierarchy

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@DRubioG

@DRubioG DRubioG commented May 15, 2026

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This improve hierarchy showing the name of the entity* and the name of the file as a label.
This also selects the icon depending of which file is going to be showed.

Note: the first file it is very difficult for me now touch it, because it follows other flow than the rest of the files.

*This is not the real entity name, is the name of the file without the extension (in a future the idea is to show the entity name)

In VHDL
Captura desde 2026-05-15 08-27-24

In verilog
Captura desde 2026-05-15 08-31-01

remove the space between others in the snippet to clarify the writing
This commit adds the next updates:
- New snippet to create fsm states
- Comment in the previous line of the constant snippet
- New snippet for signal without a previous definition (and with a previous comment), previous signal definiton with a new name "signalvalue"
- New signal to define a counter with integer value
- New line after the definition  of a library
- New library snippet to create the libries only with a numeric_std library
- Adding a new line for comment and a name in all the process snippets
- New snippet for a process(all) for a direct definition without reference to the sensity list
- New snippet for a "process begin" in testbench
- Rename the signed reference
- Fix a wrong descriptiion found in subtype
- Add a name previous in the sentence whenelse
Because netlist this doesn't viewer doesn't work well in VHDL, it is better to remove this option.
- Once change the icon depending which file is in the hierarchy
- Show as a label the name of the file
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