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26 changes: 25 additions & 1 deletion auto_package/language.yml
Original file line number Diff line number Diff line change
Expand Up @@ -3,18 +3,27 @@
configuration: "./configs/vhdl.configuration.json"
snippets: "./snippets/vhdl/vhdl.json"
aliases: ["VHDL", "vhdl"]
icon:
light: "./resources/icon/light/vhdl.svg"
dark: "./resources/icon/dark/vhdl.svg"

- id: "verilog"
extensions: [".v", ".vh", ".vl"]
configuration: "./configs/verilog.configuration.json"
snippets: "./snippets/verilog/verilog.json"
aliases: ["Verilog", "verilog"]
icon:
light: "./resources/icon/light/verilog.svg"
dark: "./resources/icon/dark/verilog.svg"

- id: "systemverilog"
extensions: [".sv", ".svh", ".SV"]
configuration: "./configs/systemverilog.configuration.json"
snippets: "./snippets/systemverilog/systemverilog.json"
aliases: ["System Verilog", "systemverilog"]
icon:
light: "./resources/icon/light/systemverilog.svg"
dark: "./resources/icon/dark/systemverilog.svg"

- id: "vcd"
extensions: [".vcd"]
Expand All @@ -33,26 +42,41 @@
configuration: "./configs/tcl.configuration.json"
snippets: "./snippets/tcl/tcl.json"
aliases: ["TCL", "tcl"]
icon:
light: "./resources/icon/light/tcl.svg"
dark: "./resources/icon/dark/tcl.svg"

- id: "ucf"
extensions: [".ucf"]
configuration: "./configs/ucfconstraints.configuration.json"
aliases: ["vivado ucf", "ucf constraints"]
icon:
light: "./resources/icon/light/ucf.svg"
dark: "./resources/icon/dark/ucf.svg"

- id: "xdc"
extensions: [".xdc", ".sdc"]
configuration: "./configs/xdcconstraints.configuration.json"
snippets: "./snippets/xdc/xdc.json"
aliases: ["vivado xdc", "xdc constraints"]
icon:
light: "./resources/icon/light/xdc.svg"
dark: "./resources/icon/dark/xdc.svg"

- id: "ldc"
extensions: [".ldc", ".pdc"]
configuration: "./configs/xdcconstraints.configuration.json"
snippets: "./snippets/xdc/xdc.json"
aliases: ["lattice constraints"]
icon:
light: "./resources/icon/light/xdc.svg"
dark: "./resources/icon/dark/xdc.svg"

- id: "TL-Verilog"
extensions: [".tlv"]
configuration: "./configs/tlverilog.configuration.json"
snippets: "./snippets/tlverilog/tlverilog.json"
aliases: ["TL-Verilog", "tlv", "Transactional-Level Verilog"]
aliases: ["TL-Verilog", "tlv", "Transactional-Level Verilog"]
icon:
light: "./resources/icon/light/verilog.svg"
dark: "./resources/icon/dark/verilog.svg"
6 changes: 3 additions & 3 deletions auto_package/templates/dependencie.nj
Original file line number Diff line number Diff line change
Expand Up @@ -7,11 +7,11 @@
"netlistsvg": "https://github.com/TerosTechnology/netlistsvg.git#hierarchy",
"open": "8.3.0",
"proper-lockfile": "4.1.1",
"semver": "7.3.5",
"semver": "^7.6.3",
"shelljs": "^0.8.3",
"tmp": "0.2.1",
"vscode-languageclient": "^9.0.1",
"xml2js": "0.4.23",
"xml2js": "^0.6.2",
"nunjucks": "^3.2.0",
"@types/nunjucks": "^3.1.4",
"tree-kill": "1.2.2",
Expand All @@ -29,7 +29,7 @@
"fast-xml-parser": "4.3.2",
"jest-html-reporter": "^3.7.0",
"js-yaml": "^4.1.0",
"json5": "2.1.3",
"json5": "^2.2.3",
"lodash": "^4.17.21",
"onml": "2.1.0",
"pyodide": "0.24.1",
Expand Down
7 changes: 6 additions & 1 deletion auto_package/templates/language_and_snippet.nj
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,12 @@
{%- if "configuration" in language %}
"configuration": "{{language["configuration"]}}",
{%- endif %}
"extensions": {{language["extensions"] | replace("'", '"')}}
"extensions": {{language["extensions"] | replace("'", '"')}}{%- if "icon" in language %},
"icon": {
"light": "{{language["icon"]["light"]}}",
"dark": "{{language["icon"]["dark"]}}"
}
{%- endif %}
}
{% set ns.counter = ns.counter + 1 %}
{%- endfor %}
Expand Down
68 changes: 41 additions & 27 deletions package.json
Original file line number Diff line number Diff line change
Expand Up @@ -38,13 +38,6 @@
},

"contributes": {
"iconThemes": [
{
"id": "teroshdl-icons",
"label": "TerosHDL File Icons",
"path": "./resources/icon/teroshdl-icon-theme.json"
}
],
"viewsContainers": {
"activitybar": [
{
Expand Down Expand Up @@ -784,21 +777,33 @@
"id": "vhdl",
"aliases": ["VHDL", "vhdl"],
"configuration": "./configs/vhdl.configuration.json",
"extensions": [".vhd", ".vho", ".vhdl", ".vhd"]
"extensions": [".vhd", ".vho", ".vhdl", ".vhd"],
"icon": {
"light": "./resources/icon/light/vhdl.svg",
"dark": "./resources/icon/dark/vhdl.svg"
}
}

,{
"id": "verilog",
"aliases": ["Verilog", "verilog"],
"configuration": "./configs/verilog.configuration.json",
"extensions": [".v", ".vh", ".vl"]
"extensions": [".v", ".vh", ".vl"],
"icon": {
"light": "./resources/icon/light/verilog.svg",
"dark": "./resources/icon/dark/verilog.svg"
}
}

,{
"id": "systemverilog",
"aliases": ["System Verilog", "systemverilog"],
"configuration": "./configs/systemverilog.configuration.json",
"extensions": [".sv", ".svh", ".SV"]
"extensions": [".sv", ".svh", ".SV"],
"icon": {
"light": "./resources/icon/light/systemverilog.svg",
"dark": "./resources/icon/dark/systemverilog.svg"
}
}

,{
Expand All @@ -825,35 +830,55 @@
"id": "tcl",
"aliases": ["TCL", "tcl"],
"configuration": "./configs/tcl.configuration.json",
"extensions": [".tcl", ".pro"]
"extensions": [".tcl", ".pro"],
"icon": {
"light": "./resources/icon/light/tcl.svg",
"dark": "./resources/icon/dark/tcl.svg"
}
}

,{
"id": "ucf",
"aliases": ["vivado ucf", "ucf constraints"],
"configuration": "./configs/ucfconstraints.configuration.json",
"extensions": [".ucf"]
"extensions": [".ucf"],
"icon": {
"light": "./resources/icon/light/ucf.svg",
"dark": "./resources/icon/dark/ucf.svg"
}
}

,{
"id": "xdc",
"aliases": ["vivado xdc", "xdc constraints"],
"configuration": "./configs/xdcconstraints.configuration.json",
"extensions": [".xdc", ".sdc"]
"extensions": [".xdc", ".sdc"],
"icon": {
"light": "./resources/icon/light/xdc.svg",
"dark": "./resources/icon/dark/xdc.svg"
}
}

,{
"id": "ldc",
"aliases": ["lattice constraints"],
"configuration": "./configs/xdcconstraints.configuration.json",
"extensions": [".ldc", ".pdc"]
"extensions": [".ldc", ".pdc"],
"icon": {
"light": "./resources/icon/light/xdc.svg",
"dark": "./resources/icon/dark/xdc.svg"
}
}

,{
"id": "TL-Verilog",
"aliases": ["TL-Verilog", "tlv", "Transactional-Level Verilog"],
"configuration": "./configs/tlverilog.configuration.json",
"extensions": [".tlv"]
"extensions": [".tlv"],
"icon": {
"light": "./resources/icon/light/verilog.svg",
"dark": "./resources/icon/dark/verilog.svg"
}
}

],
Expand Down Expand Up @@ -899,18 +924,7 @@
"mac": "command+delete",
"when": "editorTextFocus"
}
],

"configuration": {
"title": "TerosHDL",
"properties": {
"teroshdl.fileIcons.enabled": {
"type": "boolean",
"default": true,
"markdownDescription": "Enable TerosHDL file icons. To apply changes:\n1. Open Command Palette (Ctrl+Shift+P)\n2. Type 'File Icon Theme'\n3. Select 'TerosHDL File Icons' to enable or 'None' to disable"
}
}
}
]
},

"scripts": {
Expand Down
122 changes: 0 additions & 122 deletions resources/icon/teroshdl-icon-theme.json

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