MOS 6502 CPU Emulator (C++)
                              A software-based emulator for the MOS 6502 8-bit microprocessor, implemented in C++.
                              This project models the internal CPU state, instruction set, and memory access behavior to closely replicate real 6502 hardware.
                              
                              The MOS 6502 is a classic 8-bit CPU used in systems such as the NES, Apple II, and Commodore 64.
                              This emulator focuses on instruction-level accuracy, implementing the complete fetch–decode–execute cycle and all official opcodes.

                                                                              Features
                                                             Full implementation of all 151 official 6502 opcodes
                                                             Complete fetch–decode–execute pipeline
                                                             Accurate CPU state modeling:
                                                             Registers: A, X, Y
                                                             Program Counter (PC) and Stack Pointer (SP)
                                                             Processor Status flags (N, V, Z, C, D, I)
                                                             Correct handling of ADC / SBC, including decimal (BCD) mode
                                                             Implemented addressing modes:
                                                             Immediate
                                                             Zero Page
                                                             Absolute
                                                             Indexed (X / Y)
                                                             Indexed Indirect (Indirect, X)
                                                             Indirect Indexed (Indirect), Y
                                                             64 KB memory map simulation
                                                             Designed for deterministic and testable instruction execution

                                                                          Architecture
                                                      The emulator is structured around a modular CPU core:
                                                      CPU State: Registers, flags, stack, and memory
                                                      Instruction Decoder: Switch-based opcode dispatch
                                                      Execution Engine: Instruction-specific logic with precise flag updates
                                                      Addressing Mode Handlers: Isolated logic for memory access patterns
                                                      This structure keeps instruction behavior, addressing modes, and CPU state management clearly separated.

                                                                        Motivation
                                                        This project was built to deepen understanding of:
                                                        CPU architecture and instruction execution
                                                        Low-level arithmetic and flag behavior
                                                        Hardware-software interaction
                                                        Emulator design and debugging techniques