Add DSV4 GB300 1k1k STP disagg configs#1530
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Thanks for the contribution! For vLLM & SGLang, please ensure that your recipes is similar to the official vLLM recipes and/or the SGLang cookbook If it is not, please create a PR first before we can merge your single node PR into the master branch. Let's ensure that the documentation is first class such that the entire ML community can benefit from your hard work! Thank you PR authors are responsible for ensuring that after merging, all GitHub Action jobs fully pass. A lot of the time, failures are just flakes and simply re-running the failed jobs will fix it. If re-running failed jobs is attempted, PR authors are responsible for ensuring it passes. See GitHub's docs on re-running failed jobs: https://docs.github.com/en/actions/how-tos/manage-workflow-runs/re-run-workflows-and-jobs#re-running-failed-jobs-in-a-workflow As a rule of thumb, generally, PR authors should request a review & get a PR approval from the respective companies' CODEOWNERS before requesting a review from core maintainers. If additional help is needed, PR authors can reach out to core maintainers over Slack. |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=26176031180 |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=26176611225 |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=26176611225 |
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=26176611225 |
Port 9 non-MTP disagg configs from NVIDIA/srt-slurm#161: - 1p1d dep8/dep16, 1p4d, 1p6d, 2p1d dep12/dep16/dep48 - low-latency dep4/tp4 with zip overrides
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see unofficial run visualizer at https://inferencex.semianalysis.com/inference?unofficialRun=26302711476 |
Summary
Port 9 non-MTP disagg configs from NVIDIA/srt-slurm#161:
Reference: NVIDIA/srt-slurm#161