Single Cycle MIPS ISA 32-bit Processor Implementation in VHDL

Introduction

This project is a Single Cycle MIPS ISA 32-bit Processor Implementation. It is implemented using VHDL. MIPS (Microprocessor without Interlocked Pipelined Stages) is a reduced instruction set computer (RISC) instruction set architecture (ISA).

Features

• Word Size: Each word in this processor is a 32-bit.
• Memory Data Address: The memory data address ranges from 4 to 19.
• Instruction Memory Address: The instruction memory address ranges from 1 to 16.
• Memory Size: Each memory size is 16*32.
• Register File: The register file consists of 32 registers.

Schematic diagram using Active HDL

The simulation of the final project

Setup and Usage

1. Installation: Clone the repository to your local machine.
2. Configuration: No specific configuration is required.
3. Execution: Run the main VHDL file in your preferred VHDL simulator or from the command line.

Contributing

We welcome contributions from the community. If you wish to contribute, please fork the repository, make your changes, and open a pull request.