This project implements an E-voting system, which features an asynchronous BCD up counters that are connected together to count from 0 to 999 using three seven-segment displays. Each counter is designed using D flip-flops and coded in Verilog. The design has been simulated and tested through Proteus for verification.
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Asynchronous BCD Up Counter (0-9): Designed using D flip-flops to count from 0 to 9.
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Extended Counter (0-999): The whole system counts from 0 to 999 using three BCD counters connected together and three seven-segment displays controlled by the output of the flip-flops.
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Verilog Simulation: The logic of the counter has been implemented and verified using Verilog HDL.
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Proteus Simulation: The entire circuit has been connected and tested in Proteus, ensuring correct functionality of the design with the seven-segment displays.
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Clock Generator:
- A clock generator module provides the necessary clock signal to drive the flip-flops and counter logic.
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BCD Up Counter:
- The counter uses D flip-flops to asynchronously toggle bits and count from 0 to 9, incrementing each time a clock pulse is received.
- The counter extends to count up to 999, with hundreds, tens, and unit counters driving separate seven-segment displays.
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Counter to Seven-Segment Decoder:
- The decoder module converts the binary output of the counter into a format that can be displayed on the seven-segment displays.
- Three seven-segment displays show the hundreds, tens, and unit places of the count.
- The design was simulated using a testbench written in Verilog to verify the functionality of the counter.
- The waveforms were generated using simulation tools to ensure that the counter increments correctly and displays the correct values on the seven-segment display.
- The circuit was designed and simulated in Proteus to verify the connection of the flip-flops and seven-segment displays.
- The output from the D flip-flops successfully drives the seven-segment displays, counting from 0 to 999.
