Pinned Loading
-
Pipelined-RISCV-Processor
Pipelined-RISCV-Processor Public32-bit pipelined RISC-V processor implemented in Verilog with hazard detection, data forwarding, and FPGA deployment
Verilog
-
Stock-Trading-Application
Stock-Trading-Application PublicFull-stack stock trading platform built with React, Java Spring Boot, and MySQL with real-time market data and CI/CD pipeline
JavaScript
-
FPGA-Workout-Classifier
FPGA-Workout-Classifier PublicReal-time exercise detection system using a custom MLP on a Xilinx Zynq FPGA with MoveNet keypoint inference on the ARM processing system
Python
Something went wrong, please refresh the page to try again.
If the problem persists, check the GitHub status page or contact support.
If the problem persists, check the GitHub status page or contact support.