Hardware Architectures | Quantitative Systems | Software Engineering
🔗 https://github.com/Raghavan-04/Custom_Audio_SOC
🔗 https://github.com/Raghavan-04/Hardware_Accelerator
🔗 https://gitroll.io/profile/ux6xlPz2j34NorYAdef641TEA9ru1
Hardware Architectures | Quantitative Systems | Software Engineering
🔗 https://github.com/Raghavan-04/Custom_Audio_SOC
🔗 https://github.com/Raghavan-04/Hardware_Accelerator
🔗 https://gitroll.io/profile/ux6xlPz2j34NorYAdef641TEA9ru1
Synthesizable RV32IM Audio SoC featuring a centralized AMBA AXI4-Lite Router Matrix, AXI-to-APB Bridge, 1KB Data SRAM, and PWM engine. Timing-closed and physical layout verified via OpenLane (Sky130).
Verilog 2
Systolic-Tensor-Core, References the "Systolic Array" architecture used in TPUs.
C++ 2
Software-based OFDM channel estimation framework that leverages a cascaded Initial Denoising Network (IDN) and a Transformer-based model to reconstruct high-fidelity Channel State Information (CSI).
Pipelined 4-Lane SIMD Vector Core Processor in SystemVerilog. Features an industrial hybrid INT8/INT32 datapath, elastic lane FIFOs, dynamic Valid/Ready handshaking, and an automated object-oriente…
C++
This project compares single-stage and two-stage Miller-compensated operational amplifiers designed in gpdk180 technology. Key focus areas include transistor sizing, DC gain optimization, CMRR anal…
A novel strip-based Colorimetric Sensing platform for detection and measurement of Sodium in Human Sweat
HTML 2