This project implements a simplified MIPS-style CPU core integrating the program counter, ALU, and register file in Verilog
The program counter (PC) increments after each instruction, allowing the CPU to fetch the next instruction from memory.
The CPU supports two instruction formats:
R-Type
[31:26] opcode | [25:21] $s2 | [20:16] $s3 | [15:11] $s1 | [10:0] unused
I-Type
[31:26] opcode | [25:21] $s2 | [20:16] $s1 | [15:0] immediate
The CPU contains a 32-bit register file used to store and retrieve data during instruction execution.
Supported instructions include:
- Addition, subtraction, and ADDI
- Load and store
- AND, OR, and NOR
- BEQ and BNE (branch if equal and branch if not equal)
- SLT (
$s1 = ($s2 < $s3) ? 1 : 0) - EOF (program termination)
The CPU operates using a finite state machine (FSM) consisting of the following states:
- Fetch
- Decode
- Execute
- Memory Access
- Writeback
The FSM continuously cycles through these states until the termination instruction is encountered. When the termination bit is asserted, the next state is forced to the termination state.
Only load and store instructions require the Memory Access stage. All other instructions transition directly from Execute to Writeback.
The ALU is enabled during the Execute stage to perform arithmetic and logical operations. During the Memory Access stage, memory write operations are enabled for store instructions.
During the Writeback stage, the result of the operation is written to the register file, and the program counter is updated.
There is a 2 bit output status which will return:
- 0 for a successful R type instruction
- 1 for a successful I type instruction
- 2 for an overflow detection
- 3 for program termination
A 2-bit status output indicates the result of instruction execution:
0– Successful R-type instruction1– Successful I-type instruction2– Overflow detected3– Program termination
The final design meets timing requirements:
| Metric | Value |
|---|---|
| Required Time | 733.85 ps |
| Arrival Time | 733.33 ps |
| Slack | 0.52 ps |
Timing Status: MET
| Metric | Value |
|---|---|
| Total Power | 2.18 mW |
The final physical implementation consists of approximately 5,934 standard-cell instances with a total synthesized area of 813.097 μm².
| Metric | Value |
|---|---|
| Number of Ports | 847 |
| Number of Nets | 6,592 |
| Number of Cells | 5,934 |
| Number of Combinational Cells | 4,752 |
| Number of Sequential Cells | 1,175 |
| Number of Macros / Black Boxes | 0 |
| Number of Buffers/Inverters | 896 |
| Number of References | 45 |
| Area Metric | Value (μm²) |
|---|---|
| Combinational Area | 367.678 |
| Buffer/Invoker Area | 39.468 |
| Sequential Area | 445.419 |
| Macro/Black Box Area | 0.000 |
| Total Cell Area | 813.097 |
- Verilog HDL
- Synopsys Verdi
- Cadence Innovus