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Update opamp.py #2

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a4b71b1
Update opamp.py
Nimok15 Jun 10, 2026
01d6a5e
Update diff_pair_cmirrorbias.py
Nimok15 Jun 10, 2026
628bd70
Update diff_pair_cmirrorbias.py
Nimok15 Jun 10, 2026
118fbd1
Update diff_pair_cmirrorbias.py
Nimok15 Jun 10, 2026
96793e3
Update diff_pair_cmirrorbias.py
Nimok15 Jun 10, 2026
ee907ae
Update diff_pair_cmirrorbias.py
Nimok15 Jun 10, 2026
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14 changes: 10 additions & 4 deletions src/glayout/cells/composite/diffpair_cmirror_bias/diff_pair_cmirrorbias.py
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Original file line number Diff line number Diff line change
Expand Up @@ -163,7 +163,7 @@ def diff_pair_ibias(
gate_route_topmet="met3",
sd_route_topmet="met3",
rmult=rmult,
tie_layers=("met2", "met2"),
tie_layers=("met2", "met1"),
)
# cmirror routing
metal_sep = pdk.util_max_metal_seperation()
Expand Down Expand Up @@ -194,16 +194,20 @@ def diff_pair_ibias(
viaoffset=None,
)
cmirror.add_ports(srcshort.get_ports_list(), prefix="purposegndports")
_lastcol = diffpair_bias[2] - 1
# Ground the outer dummies to the welltie — same recipe as the standalone
# current_mirror cell (which passes DRC+LVS on both PDKs): met1 strap to
# the ring's met1 vertical segment.
cmirror << straight_route(pdk, cmirror.ports["A_0_dummy_L_gsdcon_top_met_W"], cmirror.ports["welltie_W_top_met_W"], glayer2="met1")
cmirror << straight_route(pdk, cmirror.ports[f"B_{_lastcol}_dummy_R_gsdcon_top_met_E"], cmirror.ports["welltie_E_top_met_E"], glayer2="met1")
# current mirror netlist — gf180 needs `dummies_tied_to_bulk=False`
# because here we use raw two_nfet_interdigitized + custom routing,
# NOT current_mirror, so the standalone-cell's straight_route from
# dummy gsdcon to welltie never gets drawn; klayout extracts the
# cmirror dummies on a per-cell floating net. sky130 magic merges
# the floating dummies into the bulk so the schematic must keep
# them tied to VB or magic counts an extra net.
## HACK: Note that this is a hack for magic LVS, and it's likely incorrect
## we probably want to fix it properly
_dummies_tied = (pdk.name.lower() == "sky130")
_dummies_tied = True
cmirror.info['netlist'] = current_mirror_netlist(
pdk,
width=diffpair_bias[0],
Expand Down Expand Up @@ -297,3 +301,5 @@ def diff_pair_ibias(
diffpair_i_flat.info['netlist'] = diff_pair_ibias_netlist(center_diffpair_comp, cmirror, antenna_diode_comp)
return diffpair_i_flat



2 changes: 1 addition & 1 deletion src/glayout/cells/composite/opamp/opamp.py
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Expand Up @@ -356,7 +356,7 @@ def opamp(
# already match an opamp top-level pin. We purge them all because
# the opamp's add_opamp_labels below re-emits the right set on
# the right metal.
["VP", "VN", "VDD1", "VDD2", "IBIAS", "VSS", "B"],
["VP", "VN", "VDD1", "VDD2", "IBIAS", "VSS", "B", "VTAIL"],
)
# add LVS pin/label rects so netgen can name-match the top-level signals
opamp_top = add_opamp_labels(opamp_top, pdk, add_output_stage=add_output_stage)
Expand Down
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