NUS-CG3207 labs · Discussions · GitHub

Recommended Vivado version
Wrangling Vivado pipipipi2002

Discussions

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Which tool is used to draw the diagram in the microarchitecture

wiiii966 started Nov 21, 2025 in Other Stuff

2
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Hardware demo not matching simulations (post implementation)

chewycj asked Nov 5, 2025 in Lab 4 · Unanswered

0
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inverting WE PC signal

Himayah628 asked Oct 28, 2025 in Lab 4 · Answered

1
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Lab 2 Demo

trunghjieu2506 asked Sep 25, 2025 in Lab 2 · Answered

2
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HelloWorld from Lab1

STeng618 asked Sep 24, 2025 in Lab 2 · Unanswered

4
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Clarification about size of S_wider, Src_A_comp, and Src_B_comp signals in ALU.v, and unconnected internal register 33->32 bit warning

roeltan asked Sep 22, 2025 in Lab 2 · Answered

2
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Best practice for self-checking testbenches without exposing internal signals

yakultbottle asked Sep 21, 2025 in Lab 2 · Answered

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Nexys 4 DDR not showing up in Vivado

winstontanjh asked Sep 10, 2025 in Lab 1 · Unanswered

1
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DSA Access Hours

trunghjieu2506 started Sep 10, 2025 in Other Stuff · Closed

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Question about simulation in Lab 1

wiiii966 asked Sep 8, 2025 in Lab 1 · Unanswered

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Upper_lower behaviour

eliztan asked Sep 7, 2025 in Lab 1 · Answered

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Expected Behaviour for Undefined "X" INSTR_MEM in AA_IROM.mem

RCPilot1604 asked Sep 2, 2025 in Lab 1 · Unanswered

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Simulation enquiry

Himayah628 asked Sep 6, 2025 in Lab 1 · Answered

2
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Strange behavior on displaying instructions from IROM.mem

wiiii966 asked Sep 5, 2025 in Lab 1 · Answered

7
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Expected behaviour when both buttons are pressed

ChingWhee asked Sep 5, 2025 in Lab 1 · Answered

1
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Regarding Simulation requirements

weiliangng asked Sep 4, 2025 in Lab 1 · Answered

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Some typos in Lab 1 Activity 1 DIP_to_LED.asm

wiiii966 asked Sep 2, 2025 in Lab 1 · Answered

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Problems with CS2100DE Lab 3 Activity 1

wiiii966 started Sep 1, 2025 in Other Stuff

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Problems about CS2100DE Lab 2

wiiii966 started Aug 31, 2025 in Other Stuff

1
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Are we using SystemVerilog or Verilog in this course?

wiiii966 started Aug 19, 2025 in Other Stuff

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Lab group forming

wiiii966 started Aug 14, 2025 in Other Stuff

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My friend built a RISC-V processor in Terraria

kxing28 started Dec 12, 2024 in Other Stuff

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Lab 4: MCycle.v will benefit from using Funct3 over MCycleOp

kxing28 asked Oct 18, 2024 in Lab 4 · Closed · Answered

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Timing issues for pipelined processor and how to debug

Rayleigh47 asked Oct 28, 2024 in Wrangling Vivado · Answered

2
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godbolt compiler uses stack pointer register.

nicholas132000 asked Oct 25, 2024 in Lab 4 · Answered

2