Feature/core arraycopy - #56
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…ore validation Migrate the standalone arraycopy measurement into vee-port/validation/core as a regression test. ArrayCopyPerformance measures aligned and misaligned System.arraycopy throughput on large byte[] buffers and asserts each against a configurable minimum-throughput system property. Configured board-neutrally for this template: buffer size 256 KB, Java heap raised to 1 MB, and both throughput thresholds left unset so the checks are no-ops on any board. RT1170 reference values (125/65 MB/s) are documented in the testsuite properties for boards that opt into enforcement.
Add a 3.7.0 CHANGELOG entry for the ArrayCopyPerformance test and a README section describing the benchmark and how to configure the throughput thresholds and buffer size. Move the detailed option documentation out of microej-testsuite-common.properties into the README, leaving a short pointer.
| core.memory.javaheap.memory=RAM | ||
| core.memory.javaheap.size=32768 | ||
| # Sized to hold the two ArrayCopyPerformance buffers (see the arraycopy section below) plus headroom. | ||
| core.memory.javaheap.size=1048576 |
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Can we keep a default value that is lower here? And document the heap requirement for the copy benchmark instead?
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I have set the default value to 64kB buffers, this will reach the typical RAM cache threshold and provide good results. So a java heap of ~160kB (32kB + 2x64kB) is enough.
In the rare cases that it is too much, it is still configurable
I also added 2 overlapping copy tests (left and right), so we now have 4 throughput tests.
Extend the ArrayCopyPerformance bench with two overlapping copies within a single buffer: destination shifted one byte right (memmove copies backwards) and one byte left (copies forwards). The bench now reports four figures (aligned, misaligned, overlap-right, overlap-left), each with its own configurable minimum-throughput threshold. The overlap pair also guards against System.arraycopy being routed to memcpy, which would corrupt overlapping data. Add a note that the measured throughputs must be compared against the memory bandwidth advertised by the silicon vendor to judge whether the port reaches the expected fraction of peak, not just clear the regression floor. Keep the README intro and test docs board-agnostic (MCU data cache, RAM bandwidth). Reset the buffer size to the 64 KB code default (drop the 256 KB override).
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