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xilinx timing constraints fix#5

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aananko wants to merge 1 commit into
MIPSfpga:masterfrom
aananko:patch-1
Open

xilinx timing constraints fix#5
aananko wants to merge 1 commit into
MIPSfpga:masterfrom
aananko:patch-1

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@aananko

@aananko aananko commented Nov 2, 2015

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Seems like the core remains untimed in Nexus4_ddr variant at least. Fix for the case.

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