DSP / FPGA / Communications Engineer
Candidate of Technical Sciences
C++ • Verilog • MATLAB/Simulink • Fixed-Point DSP • Circuit Design • Information Security
I build reproducible DSP and communication-system pipelines: from MATLAB/Simulink reference models to C++ implementations, Verilog/FPGA architecture, measurements, BER/EVM/SNR analysis, and engineering documentation.
| Stage | Engineering result |
|---|---|
| Signal / RF problem | define channel, impairments, constraints, and measurable goals |
| MATLAB / Simulink model | build readable golden reference and diagnostic plots |
| C++ implementation | create deterministic, testable, reproducible software processing |
| Fixed-point design | define Q-format, rounding, saturation, and error budget |
| Verilog / FPGA architecture | map stable DSP blocks to streaming RTL and testbenches |
| Measurement and verification | compare model, software, RTL, and real/synthetic signals |
| BER / EVM / SNR reports | turn experiments into engineering conclusions and publication-ready artifacts |
Additional portfolio structure notes are available in docs/engineering-portfolio-map.md.
| Proof artifact | Repository | What it demonstrates |
|---|---|---|
| Experiment manifests + CI checks | zynq-sdr-course | reproducible SDR labs and acceptance criteria |
| DSP test-vector strategy + benchmark schema | cpp-dsp-showcase | deterministic C++ DSP validation and performance reporting |
| SLA dashboard + timestamp comparison manifest | network-quality-assessment | measurement credibility and hardware/software timestamp analysis |
| CDC comparison flow + paper outline | optical-demodulator | IEEE-style optical DSP research workflow |
| MkDocs course site + generated figures | zynq-sdr-course | documentation automation and course UX |
- Design DSP chains for communication and measurement systems.
- Convert algorithms into hardware-aware C++ and Verilog implementations.
- Build verification flows across MATLAB, C++, RTL simulation, and real signals.
- Analyze receiver quality using BER, EVM, SNR, jitter, latency, and error-budget metrics.
- Document engineering systems so that results are reproducible, reviewable, and useful.
Research-oriented coherent optical demodulation workspace with MATLAB, C++, and Verilog layers.
Focus: chromatic-dispersion compensation, DP-QPSK processing, CDC comparison reports, BER/EVM/SNR metrics, fixed-point and RTL mapping.
Bilingual SDR course connecting signal theory, DSP, fixed-point modeling, HDL flow, RF front-end understanding, and board-level experiments.
Focus: Zynq-7020, AD9363, RTL-SDR, HDSDR, experiment manifests, CI-checked assets, reproducible IEEE-style plots.
Modern C++ DSP showcase with deterministic kernels, tests, benchmark tooling, CI, and generated engineering plots.
Focus: FIR filtering, FFT overlap-save, Goertzel detector, GCC-PHAT delay estimation, rational resampling, golden vectors, benchmark methodology.
Hardware-assisted network measurement concept based on FPGA/SFP datapath timestamping and SLA-oriented metrics.
Focus: one-way delay, jitter, packet loss, timestamp accuracy, timing error budget, SLA reports, software vs hardware timestamps.
Practical automation toolbox for repeatable Windows engineering workstation setup.
Focus: SSH, Git, CMake, Visual Studio Build Tools, deployment helpers, repeatable developer environments.
Personal engineering website and portfolio landing page.
- reproducible SDR course with hardware labs and manifest-driven experiments;
- C++ DSP benchmark and verification framework;
- optical coherent receiver research platform for CDC and BER/EVM/SNR studies;
- hardware-assisted network measurement methodology with SLA reports;
- portfolio site that connects these repositories into one engineering story.
| Area | Tools and technologies |
|---|---|
| DSP / modeling | MATLAB, Simulink, fixed-point modeling, Python |
| Software | C++, CMake, tests, CI, benchmark tooling |
| FPGA / HDL | Verilog, streaming RTL, testbenches, Xilinx-oriented flows |
| Measurement | BER, EVM, SNR, constellation analysis, jitter, latency, error budget |
| Hardware | Zynq, AD9363, RTL-SDR, optical/communication signal chains, applied electronics |
| Engineering tooling | GitHub Actions, MkDocs, documentation automation, PowerShell scripts |
- Coherent optical demodulation and chromatic-dispersion compensation.
- SDR systems from signal model to RF experiment.
- Fixed-point DSP and FPGA-ready receiver architectures.
- Hardware-assisted network and communication measurements.
- Reproducible engineering documentation and CI-generated plots.
- Candidate of Technical Sciences
- 10 years of teaching experience in higher education
- Author of 3 textbooks
- Publications, inventions, and patents in technical fields
- Strong background in circuit design and information security
- Start with a clear mathematical model.
- Keep MATLAB, C++, and RTL behavior aligned with shared vectors and metrics.
- Treat measurements, plots, and reports as part of the engineering system.
- Prefer reproducible validation over one-off demos.
- Document assumptions, limitations, and error sources explicitly.
- DSP / FPGA / SDR / optical communication discussions;
- engineering collaboration and R&D initiatives;
- communication-system and telemetry-related development;
- educational engineering content and technical documentation;
- specialized software and tooling projects.
- GitHub Pages: lay007.github.io
- Telegram: @laymob