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15 changes: 14 additions & 1 deletion HDL/source/rtl/vhdl/top.vhd
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Expand Up @@ -9,11 +9,13 @@
-- Simple test for VGA control
--
-------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;


entity top is
generic (
RES_TYPE : natural := 1;
Expand Down Expand Up @@ -157,6 +159,11 @@ architecture rtl of top is
signal dir_pixel_column : std_logic_vector(10 downto 0);
signal dir_pixel_row : std_logic_vector(10 downto 0);

type color_array is array(7 downto 0) of std_logic_vector(23 downto 0);
signal colors : color_array := (
x"ffffff", x"cccc00", x"00ccff", x"00cc00",
x"e600e6", x"ff0000", x"0000ff", x"000000" );

begin

-- calculate message lenght from font size
Expand Down Expand Up @@ -246,11 +253,17 @@ begin
blue_o => blue_o
);



-- na osnovu signala iz vga_top modula dir_pixel_column i dir_pixel_row realizovati logiku koja genereise
--dir_red
--dir_green
--dir_blue


dir_red <= colors( conv_integer( dir_pixel_column(10 downto 8) ) )( 23 downto 16 );
dir_green <= colors( conv_integer( dir_pixel_column(10 downto 8) ) )( 15 downto 8 );
dir_blue <= colors( conv_integer( dir_pixel_column(10 downto 8) ) )( 7 downto 0 );

-- koristeci signale realizovati logiku koja pise po TXT_MEM
--char_address
--char_value
Expand Down
35 changes: 1 addition & 34 deletions HDL/synthesis/lab2/_xmsgs/pn_parser.xmsgs
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Expand Up @@ -8,40 +8,7 @@
<!-- Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. -->

<messages>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/char_rom/char_rom_def.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm108MHz.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm25MHz.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm50MHz.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/coregen/dcm75MHz.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/char_rom.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/graphics_mem.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/text_mem.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/top.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/vga.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/vga_sync.vhd&quot; into library work</arg>
</msg>

<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/source/rtl/vhdl/vga_top.vhd&quot; into library work</arg>
<msg type="info" file="ProjectMgmt" num="1061" ><arg fmt="%s" index="1">Parsing VHDL file &quot;C:/materija/ra170-2013/lprs2/lab2/HDL/source/rtl/vhdl/top.vhd&quot; into library work</arg>
</msg>

</messages>
Expand Down
223 changes: 47 additions & 176 deletions HDL/synthesis/lab2/_xmsgs/xst.xmsgs
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6 changes: 3 additions & 3 deletions HDL/synthesis/lab2/iseconfig/top.xreport
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Original file line number Diff line number Diff line change
@@ -1,11 +1,11 @@
<?xml version='1.0' encoding='UTF-8'?>
<report-views version="2.0" >
<header>
<DateModified>2016-02-16T15:42:35</DateModified>
<DateModified>2016-03-14T17:27:52</DateModified>
<ModuleName>top</ModuleName>
<SummaryTimeStamp>2014-03-20T11:47:08</SummaryTimeStamp>
<SavedFilePath>//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/synthesis/lab2/iseconfig/top.xreport</SavedFilePath>
<ImplementationReportsDirectory>//samba03/nastavni_materijali/lprs2/vezbe/lab2/HDL/synthesis/lab2\</ImplementationReportsDirectory>
<SavedFilePath>C:/materija/ra170-2013/lprs2/lab2/HDL/synthesis/lab2/iseconfig/top.xreport</SavedFilePath>
<ImplementationReportsDirectory>C:/materija/ra170-2013/lprs2/lab2/HDL/synthesis/lab2\</ImplementationReportsDirectory>
<DateInitialized>2014-03-10T14:57:35</DateInitialized>
<EnableMessageFiltering>false</EnableMessageFiltering>
</header>
Expand Down
103 changes: 102 additions & 1 deletion HDL/synthesis/lab2/lab2.gise
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Expand Up @@ -22,19 +22,55 @@
<sourceproject xmlns="http://www.xilinx.com/XMLSchema" xil_pn:fileType="FILE_XISE" xil_pn:name="lab2.xise"/>

<files xmlns="http://www.xilinx.com/XMLSchema">
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="_ngo"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/map.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/par.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/trce.xmsgs"/>
<file xil_pn:fileType="FILE_XMSGS" xil_pn:name="_xmsgs/xst.xmsgs"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.bgn" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BIT" xil_pn:name="top.bit" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGDBUILD_LOG" xil_pn:name="top.bld"/>
<file xil_pn:fileType="FILE_CMD_LOG" xil_pn:name="top.cmd_log"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_DRC" xil_pn:name="top.drc" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_LSO" xil_pn:name="top.lso"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top.ncd" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGC" xil_pn:name="top.ngc"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGD" xil_pn:name="top.ngd"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGR" xil_pn:name="top.ngr"/>
<file xil_pn:fileType="FILE_PAD_MISC" xil_pn:name="top.pad"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAR_REPORT" xil_pn:name="top.par" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PCF" xil_pn:name="top.pcf" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_PROJECT" xil_pn:name="top.prj"/>
<file xil_pn:fileType="FILE_TRCE_MISC" xil_pn:name="top.ptwx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_STX" xil_pn:name="top.stx"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST_REPORT" xil_pn:name="top.syr"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_TXT_REPORT" xil_pn:name="top.twr" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_TIMING_XML_REPORT" xil_pn:name="top.twx" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_UNROUTES" xil_pn:name="top.unroutes" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_BITGEN_REPORT" xil_pn:name="top.ut" xil_pn:subbranch="FPGAConfiguration"/>
<file xil_pn:fileType="FILE_XPI" xil_pn:name="top.xpi"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_XST" xil_pn:name="top.xst"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_envsettings.html"/>
<file xil_pn:fileType="FILE_NCD" xil_pn:name="top_guide.ncd" xil_pn:origination="imported"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.map" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_MAP_REPORT" xil_pn:name="top_map.mrp" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NCD" xil_pn:name="top_map.ncd" xil_pn:subbranch="Map"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_NGM" xil_pn:name="top_map.ngm" xil_pn:subbranch="Map"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_map.xrpt"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_ngdbuild.xrpt"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_EXCEL_REPORT" xil_pn:name="top_pad.csv" xil_pn:subbranch="Par"/>
<file xil_pn:branch="Implementation" xil_pn:fileType="FILE_PAD_TXT_REPORT" xil_pn:name="top_pad.txt" xil_pn:subbranch="Par"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_par.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="top_summary.html"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="top_summary.xml"/>
<file xil_pn:fileType="FILE_WEBTALK" xil_pn:name="top_usage.xml"/>
<file xil_pn:fileType="FILE_XRPT" xil_pn:name="top_xst.xrpt"/>
<file xil_pn:fileType="FILE_HTML" xil_pn:name="usage_statistics_webtalk.html"/>
<file xil_pn:fileType="FILE_LOG" xil_pn:name="webtalk.log"/>
<file xil_pn:fileType="FILE_FITTER_REPORT" xil_pn:name="webtalk_pn.xml"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xlnx_auto_0_xdb"/>
<file xil_pn:fileType="FILE_DIRECTORY" xil_pn:name="xst"/>
</files>

Expand Down Expand Up @@ -67,10 +103,12 @@
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1455633254" xil_pn:in_ck="1697841846668819324" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2533086457361772621" xil_pn:start_ts="1455633239">
<transform xil_pn:end_ts="1457976319" xil_pn:in_ck="1697841846668819324" xil_pn:name="TRANEXT_xstsynthesize_spartan6" xil_pn:prop_ck="-2533086457361772621" xil_pn:start_ts="1457976309">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<status xil_pn:value="OutOfDateForOutputs"/>
<status xil_pn:value="OutputChanged"/>
<outfile xil_pn:name="_xmsgs/xst.xmsgs"/>
<outfile xil_pn:name="top.lso"/>
<outfile xil_pn:name="top.ngc"/>
Expand All @@ -83,6 +121,69 @@
<outfile xil_pn:name="webtalk_pn.xml"/>
<outfile xil_pn:name="xst"/>
</transform>
<transform xil_pn:end_ts="1457975915" xil_pn:name="TRAN_compileBCD2" xil_pn:prop_ck="671693640407403424" xil_pn:start_ts="1457975915">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
</transform>
<transform xil_pn:end_ts="1457976324" xil_pn:in_ck="-239586722190486182" xil_pn:name="TRANEXT_ngdbuild_FPGA" xil_pn:prop_ck="-8379684147818893659" xil_pn:start_ts="1457976319">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_ngo"/>
<outfile xil_pn:name="_xmsgs/ngdbuild.xmsgs"/>
<outfile xil_pn:name="top.bld"/>
<outfile xil_pn:name="top.ngd"/>
<outfile xil_pn:name="top_ngdbuild.xrpt"/>
</transform>
<transform xil_pn:end_ts="1457976345" xil_pn:in_ck="154288912570" xil_pn:name="TRANEXT_map_spartan6" xil_pn:prop_ck="-2489532510156203999" xil_pn:start_ts="1457976324">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/map.xmsgs"/>
<outfile xil_pn:name="top.pcf"/>
<outfile xil_pn:name="top_map.map"/>
<outfile xil_pn:name="top_map.mrp"/>
<outfile xil_pn:name="top_map.ncd"/>
<outfile xil_pn:name="top_map.ngm"/>
<outfile xil_pn:name="top_map.xrpt"/>
<outfile xil_pn:name="top_summary.xml"/>
<outfile xil_pn:name="top_usage.xml"/>
</transform>
<transform xil_pn:end_ts="1457976369" xil_pn:in_ck="182976548277359827" xil_pn:name="TRANEXT_par_spartan6" xil_pn:prop_ck="-3829590541433901613" xil_pn:start_ts="1457976345">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/par.xmsgs"/>
<outfile xil_pn:name="top.ncd"/>
<outfile xil_pn:name="top.pad"/>
<outfile xil_pn:name="top.par"/>
<outfile xil_pn:name="top.ptwx"/>
<outfile xil_pn:name="top.unroutes"/>
<outfile xil_pn:name="top.xpi"/>
<outfile xil_pn:name="top_pad.csv"/>
<outfile xil_pn:name="top_pad.txt"/>
<outfile xil_pn:name="top_par.xrpt"/>
</transform>
<transform xil_pn:end_ts="1457976395" xil_pn:in_ck="154288912438" xil_pn:name="TRANEXT_bitFile_spartan6" xil_pn:prop_ck="5341574683187206424" xil_pn:start_ts="1457976369">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/bitgen.xmsgs"/>
<outfile xil_pn:name="top.bgn"/>
<outfile xil_pn:name="top.bit"/>
<outfile xil_pn:name="top.drc"/>
<outfile xil_pn:name="top.ut"/>
<outfile xil_pn:name="usage_statistics_webtalk.html"/>
<outfile xil_pn:name="webtalk.log"/>
<outfile xil_pn:name="webtalk_pn.xml"/>
</transform>
<transform xil_pn:end_ts="1457976369" xil_pn:in_ck="154288912438" xil_pn:name="TRAN_postRouteTrce" xil_pn:prop_ck="445577401284416184" xil_pn:start_ts="1457976364">
<status xil_pn:value="SuccessfullyRun"/>
<status xil_pn:value="WarningsGenerated"/>
<status xil_pn:value="ReadyToRun"/>
<outfile xil_pn:name="_xmsgs/trce.xmsgs"/>
<outfile xil_pn:name="top.twr"/>
<outfile xil_pn:name="top.twx"/>
</transform>
</transforms>

</generated_project>
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