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1. 4bit_PRNG 4bit_PRNG Public

   This project implements a 4-bit pseudo-random number generator (PRNG) on the Basys 3 FPGA board using Verilog. The PRNG is designed using a Linear Feedback Shift Register (LFSR) with a tapped XOR f…

   Verilog

2. 1x3-Packet-Router-Verification-using-UVM 1x3-Packet-Router-Verification-using-UVM Public

   UVM-based functional verification environment for a 1x3 packet router using SystemVerilog — includes driver, monitor, scoreboard, sequences, and coverage.

   SystemVerilog