- 1 NMOS Transistor
- 1.1 Simulation on Cadence - Schematic Creation
- 1.2 Bias Point VGS = 1 V, VDS = 2 V
- 1.3 iD–vDS Characteristic (sweep of vDS for several VGS)
- 1.4 iD–vGS Characteristic (sweep of vGS for several VDS)
- 1.5 Graphical Verification of the Bias Point
- 1.6 Theoretical vs Practical Comparison
- 2 Common-Source Amplifier
- 2.1 Schematic Creation
- 2.2 Time-Domain and Frequency Simulations
- 2.3 Theoretical Calculations and Comparison
- 2.4 Sizing Adjustment for |Av| = 10 and Vout ≈ VDD/2
- 2.5 Results of the Adjustment
In this first lab, the objective was to become familiar with Cadence Virtuoso through three complementary aspects.
We started with the study of an NMOS transistor, measuring parameters at a fixed bias point (VGS = 1 V and VDS = 2 V). We then plotted the iD–vDS and iD–vGS characteristics for different voltage values, verifying consistency with the chosen operating point.
The NMOS was dimensioned with L = 0.35 μm and W = 2 μm. Parameters were extracted at VSG = 1 V and VSD = 2 V, then the static characteristics were plotted to confirm the bias point.
Finally, we designed a common-source amplifier, presenting both time-domain and frequency simulation results. The gain was compared with theoretical calculations, and the design was tuned to reach a gain of 20 dB with the output centered at VDD/2.
The NMOS test circuit was created using Cadence Virtuoso.
We opened a new schematic cell with the tech_c35b4 technology. Components were chosen as follows:
-
NMOS transistor from
PRIMLIB/Mosfets/nmos4 -
DC voltage sources from
analogLib/Sources/Independent/vdc -
Ground from
analogLib/Sources/Globals/gnd -
Figure 1.1 – Schematic for NMOS transistor study
The operating point was obtained with a DC Operating Point analysis.
At VGS = 1 V and VDS = 2 V, the following values were measured:
ID = 66.96 μA
gm = 243.7 μS
gDS = 4.601 μS
Vth = 548.2 mV
r0 = 1 / gDS = 217.344 kΩ
These reference values were used for graphical verification.
Figure 1.2 – Annotated DC operating point (VGS=1 V, VDS=2 V)
Using a DC sweep on vDS, with VGS constant, we plotted iD vs vDS.
A parametric analysis repeated the sweep for VGS ranging from 0 V to 3.3 V (step 0.3 V).
The curve corresponding to VGS ≈ 1 V shows ID ≈ 66.96 μA, consistent with the .op analysis.
By sweeping vGS while keeping VDS constant, we obtained the iD–vGS characteristic.
The sweep was repeated for VDS ranging from 0.3 V to 3.0 V (step 0.3 V).
The threshold voltage Vth is visible, with quadratic increase beyond.
At (VGS, VDS) = (1 V, 2 V), ID ≈ 66.96 μA, consistent with the .op analysis.
The bias point (VGS=1 V, VDS=2 V) was verified independently on both iD–vDS and iD–vGS curves.
In both cases, ID ≈ 66.96 μA, confirming consistency between simulation and graphical reading.
Theoretical model in saturation:
ID = 1/2 · k’n (W/L) (VGS − Vth)^2
With:
- k’n = 175 μA/V²
- W = 2 μm
- L = 0.35 μm
- Vth ≈ 0.46 V
→ Theoretical ID ≈ 145.8 μA
→ Simulation gave ID ≈ 66.96 μA
Difference explanation: real transistor models include effects ignored in the quadratic equation (carrier mobility reduction, velocity saturation, channel length modulation).
Thus, simulation reflects physical reality better, though theory provides intuition.
The amplifier was designed with:
- NMOS biased at VGS ≈ 0.76 V
- Load resistance RL = 16 kΩ
- W = 22 μm, L = 2 μm
- Output taken at the drain
This ensures the output is centered near VDD/2.
Figure 2.1 – Common-source amplifier schematic
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Transient simulation: with input sine (10 mVpp), output showed ≈57 mVpp with 180° phase inversion.
Gain ≈ -5.7. -
AC analysis: with Vin = 1 V AC, Bode plot confirmed ≈ 15 dB gain at low frequency.
Small-signal model:
Av = - gm (RL || r0) = - gm·RL / (1 + gds·RL)
From .op annotations: gm, gds → compute r0.
→ Theoretical gain ≈ -5.7 (≈15 dB).
→ Simulation confirmed ≈ 15 dB.
Small differences come from non-idealities (channel length modulation, finite input amplitude, sweep step).
Target: gain |Av| = 10 (20 dB) with output centered at VDD/2.
Steps:
- Choose RL = 10 kΩ → ID ≈ VDD / (2·RL) ≈ 165 μA.
- With λ ≈ 0.069 V⁻¹ → r0 ≈ 88 kΩ → RL || r0 ≈ 9.2 kΩ.
- Target gm ≈ 1.1 mS.
- Vov ≈ 0.30 V → VGS ≈ 0.85 V.
- From kn′ = 175 μA/V² → W/L ≈ 20.5 → choose L=2 μm, W≈41 μm.
Simulation confirmed output centering at VDD/2 and |Av|≈10.
Final parameters:
VGS,DC = 0.83 V RL = 11 kΩ W = 44 μm (L = 2 μm)
At this point:
- Output ≈ VDD/2
- Frequency response plateau at Av ≈ 20 dB
- Consistent with theoretical estimation
Figure 2.4 – Operating point (.op) annotations
Figure 2.5 – Frequency gain (≈ 20 dB plateau at low frequency)
This lab was a valuable exercise combining microelectronics and analog design.
It demonstrated:
- NMOS transistor modeling and biasing
- Graphical and theoretical verification of transistor characteristics
- Common-source amplifier design and analysis
- Iterative sizing to meet gain and output constraints
The work highlighted differences between simplified models and real simulations, emphasizing the importance of accurate device modeling in integrated circuit design.