Gatewiz

Digital Logic Design and Simulation using Verilog and SystemVerilog

Objective

To design, simulate, and test digital logic systems using Verilog HDL and SystemVerilog, including structured testbenches and waveform-based debugging

Project Components

1. Combinational & Sequential Logic

• Basic gates, multiplexers, adders, decoders
• Latches, D flip-flops, shift registers, counters

2. Finite State Machines (FSMs)

• Moore and Mealy machines for sequence detection and control logic
• Synchronous state transitions and state encoding

3. Verilog-based Digital Clock

• Real-time hour-minute-second display
• Alarm setting with enable/disable functionality
• Clock division logic for real-time simulation

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Verification Strategy

Simulation Tools

• GTKWave for waveform inspection
• Icarus Verilog for compiling and simulating RTL and testbenches

Testbench Design

• Developed using SystemVerilog and Object-Oriented Programming (OOP) principles
• Reusable, modular architecture for scalable testing
• Automatic stimulus generation and result checking

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