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refactor: consolidate host-side C++ into a clean sim/ tree#1

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HirunaVishwamith merged 1 commit into
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refactor/host-cpp-reorg
Jun 21, 2026
Merged

refactor: consolidate host-side C++ into a clean sim/ tree#1
HirunaVishwamith merged 1 commit into
mainfrom
refactor/host-cpp-reorg

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Summary

Reorganizes the host-side C++ — golden-model emulator, Verilator wrapper, and lock-step/profile harnesses — from three scattered top-level trees (emulator/, simulator/src/, harnesses/) into one coherent sim/ tree. Behavior-preserving: the ISA regression stays 83/84 (same sole failure, rv64ui-p-fence_i) and vvadd-q4 PASS at every step.

Structure

Old New
emulator/src/ sim/emulator/
simulator/src/ sim/rtl/
simulator/src/simulator.h sim/rtl/rtl_model.h
harnesses/ sim/harness/
emulator/riscv-tests/ sim/tests/riscv-isa/
Image / qemu.dtb / boot.bin sim/data/

Cleanups

  • Split the 2231-line hart.h into a ~340-line table-of-contents plus hart_{csr,trap,alu,memory,execute}.inc fragments, each #included at its exact original location (token-identical after preprocessing, so lock-step is provably unchanged). Free TTY helpers → terminal.h; include guard added to clint.h.
  • Deduped harness boilerplate (arg parsing, image loading, completion checks) into sim/harness/common/{args,image,completion}.h under namespace harness.
  • Rewrote rtl_model.h: added the missing include guard, replaced four hand-unrolled 32-case register switch ladders with a table-driven reg(i), merged the near-duplicate step/step_nodump, dropped commented-out dead code.
  • Deleted dead files: emulator-v1.h (1883 lines), rv_tests.cpp, bench.cpp, run.sh, simulator.txt, bbl_nommu.dump, format.gtkw, support_prog.cpp, the redundant standalone emulator/Makefile, and committed build artifacts.
  • Fixed a pre-existing bug: make emu never worked (emulator_linux.cpp ignored argv and opened a non-existent default Image); it now honors argv[1].
  • Rewired mk/config.mk + mk/run.mk paths, consolidated .gitignore, updated the README layout. CI is unchanged (it drives everything through make).

Verification

Check Result
make isa 83/84 — identical to baseline
make test-q4 vvadd-q4 PASS
make runLockStep vvadd-s1 pass
make profile BENCH=vvadd-s1 completes + JSON written
make emu BENCH=vvadd-s1 runs (now fixed)
All 7 harnesses compile clean, no warnings

make clean && make sim (full sbt+Verilator rebuild) was intentionally not run locally since the RTL is untouched — CI exercises that path.

🤖 Generated with Claude Code

Reorganize the emulator, Verilator wrapper, and harnesses from three
scattered top-level trees into one coherent sim/ tree. Behavior-preserving:
ISA regression stays 83/84 (sole fail rv64ui-p-fence_i) and vvadd-q4 PASS.

Structure:
- emulator/src/ -> sim/emulator/, simulator/src/ -> sim/rtl/,
  harnesses/ -> sim/harness/, riscv-tests/ -> sim/tests/riscv-isa/,
  runtime data (Image/qemu.dtb/boot.bin) -> sim/data/
- simulator.h -> sim/rtl/rtl_model.h

Cleanups:
- Split the 2231-line hart.h into a ~340-line table-of-contents plus
  hart_{csr,trap,alu,memory,execute}.inc fragments included at their exact
  original location (token-identical after preprocessing); free TTY helpers
  -> terminal.h; add include guard to clint.h.
- Dedup harness boilerplate (arg parsing, image loading, completion checks)
  into sim/harness/common/{args,image,completion}.h under namespace harness.
- Rewrite rtl_model.h: add include guard, replace four 32-case register
  switches with a table-driven reg(i), merge step/step_nodump, drop dead code.
- Delete dead files: emulator-v1.h, rv_tests.cpp, bench.cpp, run.sh,
  simulator.txt, bbl_nommu.dump, format.gtkw, support_prog.cpp, standalone
  emulator/Makefile.
- Fix make emu: emulator_linux.cpp now honors argv[1] instead of opening a
  non-existent default Image.
- Rewire mk/config.mk + mk/run.mk paths, consolidate .gitignore, update README.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
@HirunaVishwamith HirunaVishwamith merged commit 2b123ed into main Jun 21, 2026
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