refactor: consolidate host-side C++ into a clean sim/ tree#1
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Reorganize the emulator, Verilator wrapper, and harnesses from three
scattered top-level trees into one coherent sim/ tree. Behavior-preserving:
ISA regression stays 83/84 (sole fail rv64ui-p-fence_i) and vvadd-q4 PASS.
Structure:
- emulator/src/ -> sim/emulator/, simulator/src/ -> sim/rtl/,
harnesses/ -> sim/harness/, riscv-tests/ -> sim/tests/riscv-isa/,
runtime data (Image/qemu.dtb/boot.bin) -> sim/data/
- simulator.h -> sim/rtl/rtl_model.h
Cleanups:
- Split the 2231-line hart.h into a ~340-line table-of-contents plus
hart_{csr,trap,alu,memory,execute}.inc fragments included at their exact
original location (token-identical after preprocessing); free TTY helpers
-> terminal.h; add include guard to clint.h.
- Dedup harness boilerplate (arg parsing, image loading, completion checks)
into sim/harness/common/{args,image,completion}.h under namespace harness.
- Rewrite rtl_model.h: add include guard, replace four 32-case register
switches with a table-driven reg(i), merge step/step_nodump, drop dead code.
- Delete dead files: emulator-v1.h, rv_tests.cpp, bench.cpp, run.sh,
simulator.txt, bbl_nommu.dump, format.gtkw, support_prog.cpp, standalone
emulator/Makefile.
- Fix make emu: emulator_linux.cpp now honors argv[1] instead of opening a
non-existent default Image.
- Rewire mk/config.mk + mk/run.mk paths, consolidate .gitignore, update README.
Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
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Summary
Reorganizes the host-side C++ — golden-model emulator, Verilator wrapper, and lock-step/profile harnesses — from three scattered top-level trees (
emulator/,simulator/src/,harnesses/) into one coherentsim/tree. Behavior-preserving: the ISA regression stays 83/84 (same sole failure,rv64ui-p-fence_i) and vvadd-q4 PASS at every step.Structure
emulator/src/sim/emulator/simulator/src/sim/rtl/simulator/src/simulator.hsim/rtl/rtl_model.hharnesses/sim/harness/emulator/riscv-tests/sim/tests/riscv-isa/Image/qemu.dtb/boot.binsim/data/Cleanups
hart.hinto a ~340-line table-of-contents plushart_{csr,trap,alu,memory,execute}.incfragments, each#included at its exact original location (token-identical after preprocessing, so lock-step is provably unchanged). Free TTY helpers →terminal.h; include guard added toclint.h.sim/harness/common/{args,image,completion}.hundernamespace harness.rtl_model.h: added the missing include guard, replaced four hand-unrolled 32-case registerswitchladders with a table-drivenreg(i), merged the near-duplicatestep/step_nodump, dropped commented-out dead code.emulator-v1.h(1883 lines),rv_tests.cpp,bench.cpp,run.sh,simulator.txt,bbl_nommu.dump,format.gtkw,support_prog.cpp, the redundant standaloneemulator/Makefile, and committed build artifacts.make emunever worked (emulator_linux.cppignoredargvand opened a non-existent defaultImage); it now honorsargv[1].mk/config.mk+mk/run.mkpaths, consolidated.gitignore, updated the README layout. CI is unchanged (it drives everything throughmake).Verification
make isamake test-q4make runLockStepmake profile BENCH=vvadd-s1make emu BENCH=vvadd-s1make clean && make sim(full sbt+Verilator rebuild) was intentionally not run locally since the RTL is untouched — CI exercises that path.🤖 Generated with Claude Code