Mendel

Mendel is an in-storage heterogeneous acceleration framework for long-read genome mapping. It combines near-NAND seeding, in-memory post-matching filtering, and FPGA-based pre-alignment filtering and alignment inside a single SSD, minimising data movement and energy consumption.

The repository contains two main components: a Python emulation platform for performance and energy modelling, and SystemVerilog RTL for the hardware implementation targeting the Samsung SmartSSD (AMD Kintex UltraScale+ KU15P).

Quick Start

# 1. Set up the environment
cp env.sh.example env.sh   # if starting fresh, or edit env.sh directly
source env.sh

# 2. Run the emulation platform
cd emulation/
python benchmark_10mb.py

Environment Setup

All tool paths and external dependency locations are configured in env.sh at the repository root. Source it before running any synthesis or HLS flow:

source /path/to/mendel/env.sh

Key variables:

Variable	Description
MENDEL_ROOT	Repository root (set automatically)
VIVADO_BIN	Path to the vivado executable
VITIS_HLS_BIN	Path to the vitis_hls executable
DC_SHELL_BIN	Path to the dc_shell executable
MENDEL_PDK_TARGET_LIB	Timing library (.db) for ASIC synthesis
MENDEL_SRAM_LIB	SRAM macro libraries (.db) for D-SOFT PIM
SNEAKY_SNAKE_DIR	SneakySnake clone root
WFA2_LIB_DIR	WFA2-lib clone root
MENDEL_WFA_HLS_IP_DIR	Exported wfa_core Vivado IP directory

See env.sh for the full list and inline documentation.

Repository Layout

mendel/
├── env.sh          ← Environment variables (tool paths, PDK paths, deps)
├── emulation/      ← Transaction-level Python emulation platform
├── hardware/       ← SystemVerilog RTL and synthesis scripts
└── data/           ← Input datasets and reference genomes

Emulation (emulation/)

Transaction-level Python models of four accelerator configurations for genome read mapping. Models latency, throughput, and energy — not functional correctness.

Configuration	Description
darwin_real	Darwin GACT/D-SOFT on a commodity PCIe Gen3 SSD
darwin_ideal	Darwin on a high-end PCIe Gen4 SSD (no I/O overhead)
darwin_genstore	Darwin Real + GenStore in-storage pre-filter
mendel_accurate / mendel_noisy	Full Mendel in-storage pipeline on Samsung SmartSSD

cd emulation/

# Single accelerator run
python main_integrated.py --accelerator mendel_accurate --synthetic-dataset 10 10

# 4-way comparison
python compare_darwin.py --dataset-size 10 --sequence-length 10

# Full sweep: 4 accelerators × 9 read lengths (2–50 kbp)
python benchmark_10mb.py

See emulation/README.md for architecture details and emulation/USAGE_GUIDE.md for the full CLI reference.

Hardware (hardware/)

SystemVerilog RTL for the Mendel in-storage pipeline, organised by accelerator location within the SSD.

hardware/
├── asic/
│   ├── seeding_core/    ← Near-NAND seeding accelerators (32 SC/channel × 8 channels)
│   └── dsoft_pim/       ← Near-LPDDR D-SOFT in-memory match and filter
├── fpga/                ← FPGA subsystem (KU15P): PAF + alignment
└── tcl/                 ← Synthesis scripts (DC Shell for ASIC, Vivado for FPGA)

ASIC — Seeding Core (asic/seeding_core/)

Lightweight flash-channel accelerators that compute minimizer seeds from 2048 bp chunks. 32 instances per channel, 256 total across 8 channels, running at 750 MHz.

Synthesise with:

source env.sh
dc_shell -f hardware/tcl/synth_seeding_core.tcl | tee logs/synth_seeding_core.log

ASIC — D-SOFT PIM (asic/dsoft_pim/)

Processing-in-memory accelerator inside the LPDDR3 DRAM. Performs index lookup and D-SOFT bin updates entirely within the DRAM boundary, outputting filtered mapping positions to the SSD processor.

Synthesise with:

source env.sh
dc_shell -f hardware/tcl/synth_dsoft_pim.tcl | tee logs/synth_dsoft_pim.log

FPGA (fpga/)

KU15P subsystem handling the two compute-intensive pipeline stages:

• Snake-on-Chip array — 32 SneakySnake PE instances for pre-alignment filtering (PAF). Half the instances are dispatched per request.
• WFA aligner array — 4 Wavefront Alignment cores for final sequence alignment, reading reference and query data from on-board DDR4.
• Accept Logic — applies the BubbleFilter decision and replies to the SSD processor over PCIe.
• Query Logic — parses incoming PCIe packets and dispatches to the correct accelerator pool.

Synthesise with:

source env.sh
vivado -mode batch -source hardware/tcl/synth_mendel_fpga.tcl

See hardware/fpga/README.md for the full block diagram, parameter table, IP dependencies, and resource estimates.